diff options
| author | Ravikumar Kattekola <rk@ti.com> | 2015-01-12 15:41:32 +0530 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2015-01-27 15:33:14 +0530 |
| commit | c95ca92ca9a0ab401283df6a54cad227d9be2666 (patch) | |
| tree | 25336ef4979947b1d5e81d622ff9766af18013d0 /arch | |
| parent | 7dca540329010694ca5f2508bf2359cccabb6228 (diff) | |
ARM: DRA7x: Clock: Fix dpll rate calculation in bypass mode
On DRA7x, clk_get_rate() on a DPLL clk in kernel returns zero
in bypass mode.
This is because the condtional check for bypass mode
in omap2_get_dpll_rate() is missing DRA7xx platform.
Fix this by adding soc_is_dra7xx() to the check. While at it fix
the omap2_init_dpll_parent() as well.
The logic behind the check is
On POR most of the DPLLs come in bypass mode,
if a PLL is in bypass at kernel init, the code in
omap2_get_dpll_rate() will not realize this and will try to calculate
the clock rate using the multiplier and the divider, resulting in
errors.
Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/clkt_dpll.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 60947c54fae..cbc3ee3a950 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -209,7 +209,8 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || + soc_is_dra7xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) @@ -255,7 +256,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return __clk_get_rate(dd->clk_bypass); - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || + soc_is_dra7xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) |