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authorRavikumar Kattekola <rk@ti.com>2015-01-12 15:41:34 +0530
committerLokesh Vutla <lokeshvutla@ti.com>2015-01-27 15:35:37 +0530
commitd3e2aef040080a18162fbe247636c1b0f1025940 (patch)
tree1902ff9479af49dddb978feea10dec368cb31d99 /arch
parent3393f0a296154b6fa331235b6f1984f719eaf2fc (diff)
ARM: OMAP5: Clock: Fix dpll rate calculation in bypass mode
On OMAP54xx, clk_get_rate() on a DPLL clk in kernel returns zero in bypass mode. This is because the condtional check for bypass mode in omap2_get_dpll_rate() is missing OMAP5x platform. Fix this by adding soc_is_omap54xx() to the check. While at it fix the omap2_init_dpll_parent() as well. The logic behind the check is On POR most of the DPLLs come in bypass mode, if a PLL is in bypass at kernel init, the code in omap2_get_dpll_rate() will not realize this and will try to calculate the clock rate using the multiplier and the divider, resulting in errors. Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cbc3ee3a950..f595d812f82 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -210,7 +210,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return 1;
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
- soc_is_dra7xx()) {
+ soc_is_dra7xx() || soc_is_omap54xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return __clk_get_rate(dd->clk_bypass);
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
- soc_is_dra7xx()) {
+ soc_is_dra7xx() || soc_is_omap54xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)