diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_7xx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 5ae755c6c69..75df5757869 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1114,6 +1114,40 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = { }; /* + * 'gpu' class + * 2d/3d graphics accelerator + */ + +static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_gpu_hwmod_class = { + .name = "gpu", + .sysc = &dra7xx_gpu_sysc, +}; + +static struct omap_hwmod dra7xx_gpu_hwmod = { + .name = "gpu", + .class = &dra7xx_gpu_hwmod_class, + .clkdm_name = "gpu_clkdm", + .main_clk = "gpu_core_gclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'hdq1w' class * */ @@ -1620,6 +1654,22 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { .sysc = &dra7xx_mcasp_sysc, }; +/* mcasp2 */ +static struct omap_hwmod dra7xx_mcasp2_hwmod = { + .name = "mcasp2", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp2_ahclkx_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* mcasp3 */ static struct omap_hwmod dra7xx_mcasp3_hwmod = { .name = "mcasp3", @@ -1636,6 +1686,22 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = { }, }; +/* mcasp6 */ +static struct omap_hwmod dra7xx_mcasp6_hwmod = { + .name = "mcasp6", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp6_ahclkx_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* * 'mmc' class * @@ -3246,6 +3312,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + /* l4_per2 -> mcasp3 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { .master = &dra7xx_l4_per2_hwmod, @@ -3254,6 +3328,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = { { .pa_start = 0x48078000, @@ -3354,6 +3436,45 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = { + { + .name = "klio", + .pa_start = 0x56000000, + .pa_end = 0x56001fff, + }, + { + .name = "hydra2", + .pa_start = 0x56004000, + .pa_end = 0x56004fff, + }, + { + .name = "klio_0", + .pa_start = 0x56008000, + .pa_end = 0x56009fff, + }, + { + .name = "klio_1", + .pa_start = 0x5600c000, + .pa_end = 0x5600dfff, + }, + { + .name = "klio_hl", + .pa_start = 0x5600fe00, + .pa_end = 0x5600ffff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> gpu */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_gpu_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_gpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { { .pa_start = 0x480b2000, @@ -4106,7 +4227,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__hdmi, &dra7xx_l3_main_1__aes, &dra7xx_l3_main_1__sha0, + &dra7xx_l4_per2__mcasp2, &dra7xx_l4_per2__mcasp3, + &dra7xx_l4_per2__mcasp6, &dra7xx_l4_per1__elm, &dra7xx_l4_wkup__gpio1, &dra7xx_l4_per1__gpio2, @@ -4117,6 +4240,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__gpio7, &dra7xx_l4_per1__gpio8, &dra7xx_l3_main_1__gpmc, + &dra7xx_l3_main_1__gpu, &dra7xx_l4_per1__hdq1w, &dra7xx_l4_per1__i2c1, &dra7xx_l4_per1__i2c2, |