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authorSumit Semwal <sumit.semwal@linaro.org>2018-01-18 11:06:20 +0530
committerSumit Semwal <sumit.semwal@linaro.org>2018-01-18 11:06:20 +0530
commit9aff7a0edeff3e89401a33927824b7a96eaab09b (patch)
tree16f2769d8a0c95f20b78200f40c8d806e800fa28
parentbee5a2c619012ffdd7f0f0b377d34e07fcb8c4f1 (diff)
parentb4fbc4af65e2541df4e2140fd2a6eb988a4f3137 (diff)
Merge remote-tracking branch 'docularxu/working-hikey-tracking-dts-v4.4' into lts-4.4.y-hikey
Diffstat
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts388
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi69
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi820
-rw-r--r--arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi727
-rwxr-xr-xinclude/dt-bindings/pinctrl/hisi.h59
5 files changed, 2059 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 8d43a0fce522..c36bd3aeea82 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -6,11 +6,10 @@
*/
/dts-v1/;
-
-/*Reserved 1MB memory for MCU*/
-/memreserve/ 0x05e00000 0x00100000;
+#include <dt-bindings/gpio/gpio.h>
#include "hi6220.dtsi"
+#include "hikey-pinctrl.dtsi"
/ {
model = "HiKey Development Board";
@@ -27,8 +26,389 @@
stdout-path = "serial3:115200n8";
};
+ /*
+ * Reserve below regions from memory node:
+ *
+ * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
+ * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
+ * 0x06df,f000 - 0x06df,ffff: Mailbox message data
+ * 0x0740,f000 - 0x0740,ffff: MCU firmware section
+ * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
+ * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
+ */
memory@0 {
device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
+ reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
+ <0x00000000 0x05f00000 0x00000000 0x00001000>,
+ <0x00000000 0x05f02000 0x00000000 0x00efd000>,
+ <0x00000000 0x06e00000 0x00000000 0x0060f000>,
+ <0x00000000 0x07410000 0x00000000 0x1aaf0000>,
+ <0x00000000 0x22000000 0x00000000 0x1c000000>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ pstore: pstore@0x21f00000 {
+ no-map;
+ reg = <0x0 0x21f00000 0x0 0x00100000>; /* pstore/ramoops buffer */
+ };
+
+ ramoops {
+ compatible = "ramoops";
+ memory-region = <&pstore>;
+ record-size = <0x0 0x00020000>;
+ console-size = <0x0 0x00020000>;
+ ftrace-size = <0x0 0x00020000>;
+ };
+
+ reboot_reason: reboot-reason@05f01000 {
+ compatible = "linux,reboot-reason-sram";
+ reg = <0x0 0x05F01000 0x0 0x4>;
+ reason,none = <0x77665501>;
+ reason,bootloader = <0x77665500>;
+ reason,recovery = <0x77665502>;
+ reason,oem = <0x6f656d00>;
+ };
+
+ soc {
+ i2c0: i2c@f7100000 {
+ status = "ok";
+ };
+
+ i2c1: i2c@f7101000 {
+ status = "ok";
+ };
+
+ uart1: uart@f7111000 {
+ status = "ok";
+ };
+
+ uart2: uart@f7112000 {
+ status = "ok";
+ };
+
+ uart3: uart@f7113000 {
+ status = "ok";
+ };
+
+ dwmmc_2: dwmmc2@f723f000 {
+ ti,non-removable;
+ non-removable;
+ /* WL_EN */
+ vmmc-supply = <&wlan_en_reg>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1835";
+ reg = <2>; /* sdio func num */
+ /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ wlan_en_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ /* WLAN_EN GPIO */
+ gpio = <&gpio0 5 0>;
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ hisi-ion@0 {
+ compatible = "hisilicon,ion";
+
+ heap_sys_user@0 {
+ heap-name = "sys_user";
+ heap-range = <0x0 0x0>;
+ heap-type = "ion_system";
+ };
+
+ heap_sys_contig@0 {
+ heap-name = "sys_contig";
+ heap-range = <0x0 0x0>;
+ heap-type = "ion_system_contig";
+ };
+
+ heap_cma@0 {
+ heap-name = "cma";
+ heap-range = <0x0 0x0>;
+ heap-type = "ion_cma";
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ user_led1 {
+ label = "user_led4";
+ gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "user_led3";
+ gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
+ linux,default-trigger = "mmc0";
+ };
+
+ user_led3 {
+ label = "user_led2";
+ gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
+ linux,default-trigger = "mmc1";
+ };
+
+ user_led4 {
+ label = "user_led1";
+ gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
+ linux,default-trigger = "cpu0";
+ };
+
+ wlan_active_led {
+ label = "wifi_active";
+ gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "bt_active";
+ gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
+ linux,default-trigger = "hci0rx";
+ default-state = "off";
+ };
+ };
+
+ kim {
+ compatible = "kim";
+ pinctrl-names = "default";
+ pinctrl-0 = <>; /* FIXME: add BT PCM pinctrl here */
+ /*
+ * FIXME: The following is complete CRAP since
+ * the vendor driver doesn't follow the gpio
+ * binding. Passing in a magic Linux gpio number
+ * here until we fix the vendor driver.
+ */
+ /* BT_EN: BT_REG_ON_GPIO1_7 */
+ nshutdown_gpio = <503>;
+ dev_name = "/dev/ttyAMA1";
+ flow_cntrl = <1>;
+ baud_rate = <3000000>;
+ };
+
+ btwilink {
+ compatible = "btwilink";
+ };
+
+ pmic: pmic@f8000000 {
+ compatible = "hisilicon,hi655x-pmic";
+ reg = <0x0 0xf8000000 0x0 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ ponkey:ponkey@b1{
+ compatible = "hisilicon,hi6552-powerkey";
+ interrupt-parent = <&pmic>;
+ interrupts = <6 0>, <5 0>, <4 0>;
+ interrupt-names = "down", "up", "hold 4s";
+ };
+
+ regulators {
+ ldo2: LDO2 {
+ regulator-name = "LDO2_2V8";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo7: LDO7 {
+ regulator-name = "LDO7_SDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo10: LDO10 {
+ regulator-name = "LDO10_2V85";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <360>;
+ };
+
+ ldo13: LDO13 {
+ regulator-name = "LDO13_1V8";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo14: LDO14 {
+ regulator-name = "LDO14_2V8";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo15: LDO15 {
+ regulator-name = "LDO15_1V8";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo17: LDO17 {
+ regulator-name = "LDO17_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo19: LDO19 {
+ regulator-name = "LDO19_3V0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <360>;
+ };
+
+ ldo21: LDO21 {
+ regulator-name = "LDO21_1V8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo22: LDO22 {
+ regulator-name = "LDO22_1V2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+ };
+ };
+};
+
+&ade {
+ status = "ok";
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-gpio = <&gpio0 1 0>;
+ status = "ok";
+
+ ports {
+ /* 1 for output port */
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dsi_out0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&adv7533_in>;
+ };
+
+ dsi_out1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&panel0_in>;
+ };
+ };
+ };
+
+ /* For panel reg's value should >= 1 */
+ panel@1 {
+ compatible = "innolux,n070icn-pb1";
+ reg = <1>;
+ power-on-delay= <50>;
+ reset-delay = <100>;
+ init-delay = <100>;
+ panel-width-mm = <58>;
+ panel-height-mm = <103>;
+ pwr-en-gpio = <&gpio2 1 0>;
+ bl-en-gpio = <&gpio2 3 0>;
+ pwm-gpio = <&gpio12 7 0>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&dsi_out1>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+
+ adv7533: adv7533@39 {
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 2>;
+ pd-gpio = <&gpio0 4 0>;
+ adi,dsi-lanes = <4>;
+ adi,disable-timing-generator;
+
+ port {
+ adv7533_in: endpoint {
+ remote-endpoint = <&dsi_out0>;
+ };
+ };
+ };
+ };
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+
+ tp: tp@8{
+ compatible = "FocalTech,ft5506";
+ reg = <0x38>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <7 2>;
+ rst-gpio = <&gpio9 1 1>;
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+
+ icn6201: icn6201@5a{
+ compatible = "ChipOne,icn6201";
+ reg = <0x2d>;
+ };
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+
+ spidev@0 {
+ compatible = "linux,spidev";
+ spi-max-frequency = <500000>;
+ reg = <0>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi
new file mode 100644
index 000000000000..6dfc49332b4f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi
@@ -0,0 +1,69 @@
+/*
+ * Hikey specific energy cost model data.
+ */
+
+/* static struct idle_state idle_states_cluster_a53[] = { */
+/* { .power = 47 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
+/* { .power = 47 }, /\* WFI *\/ */
+/* { .power = 47 }, /\* cpu-sleep-0 *\/ */
+/* { .power = 0 }, /\* cluster-sleep-0 *\/ */
+/* }; */
+
+/* static struct capacity_state cap_states_cluster_a53[] = { */
+/* /\* Power per cluster *\/ */
+/* { .cap = 178, .power = 16, }, /\* 200 MHz *\/ */
+/* { .cap = 369, .power = 29, }, /\* 432 MHz *\/ */
+/* { .cap = 622, .power = 47, }, /\* 729 MHz *\/ */
+/* { .cap = 819, .power = 75, }, /\* 960 MHz *\/ */
+/* { .cap = 1024, .power = 112, }, /\* 1200 Mhz *\/ */
+/* }; */
+
+/* static struct idle_state idle_states_core_a53[] = { */
+/* { .power = 15 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
+/* { .power = 15 }, /\* WFI *\/ */
+/* { .power = 0 }, /\* cpu-sleep-0 *\/ */
+/* { .power = 0 }, /\* cluster-sleep-0 *\/ */
+/* }; */
+
+/* static struct capacity_state cap_states_core_a53[] = { */
+/* /\* Power per cpu *\/ */
+/* { .cap = 178, .power = 69, }, /\* 200 MHz *\/ */
+/* { .cap = 369, .power = 124, }, /\* 432 MHz *\/ */
+/* { .cap = 622, .power = 224, }, /\* 729 MHz *\/ */
+/* { .cap = 819, .power = 367, }, /\* 960 MHz *\/ */
+/* { .cap = 1024, .power = 670, }, /\* 1200 Mhz *\/ */
+/* }; */
+
+energy-costs {
+ CPU_COST: core-cost {
+ busy-cost-data = <
+ 178 69
+ 369 124
+ 622 224
+ 819 367
+ 1024 670
+ >;
+ idle-cost-data = <
+ 15
+ 15
+ 0
+ 0
+ >;
+ };
+
+ CLUSTER_COST: cluster-cost {
+ busy-cost-data = <
+ 178 16
+ 369 29
+ 622 47
+ 819 75
+ 1024 112
+ >;
+ idle-cost-data = <
+ 47
+ 47
+ 47
+ 0
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488a0e86..18c92b3daf5b 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -6,6 +6,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi6220-clock.h>
+#include <dt-bindings/pinctrl/hisi.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/reset/hisi,hi6220-resets.h>
/ {
compatible = "hisilicon,hi6220";
@@ -53,11 +56,43 @@
};
};
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <700>;
+ exit-latency-us = <250>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER_SLEEP: cluster-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ clocks = <&stub_clock 0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cooling-min-level = <4>;
+ cooling-max-level = <0>;
+ #cooling-cells = <2>; /* min followed by max */
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
+ dynamic-power-coefficient = <311>;
};
cpu1: cpu@1 {
@@ -65,6 +100,10 @@
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
};
cpu2: cpu@2 {
@@ -72,6 +111,10 @@
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
};
cpu3: cpu@3 {
@@ -79,6 +122,10 @@
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
};
cpu4: cpu@100 {
@@ -86,6 +133,10 @@
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
};
cpu5: cpu@101 {
@@ -93,6 +144,10 @@
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
};
cpu6: cpu@102 {
@@ -100,6 +155,10 @@
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
};
cpu7: cpu@103 {
@@ -107,6 +166,51 @@
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
+ };
+
+ CLUSTER0_L2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ CLUSTER1_L2: l2-cache1 {
+ compatible = "cache";
+ };
+
+ /include/ "hi6220-sched-energy.dtsi"
+ };
+
+ cpu_opp_table: cpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <208000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <500000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <432000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <500000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <729000000>;
+ opp-microvolt = <1090000>;
+ clock-latency-ns = <500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1180000>;
+ clock-latency-ns = <500000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1330000>;
+ clock-latency-ns = <500000>;
};
};
@@ -135,8 +239,15 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
+ #sound-dai-cells = <0>;
+ interrupt-parent = <&gic>;
ranges;
+ sram: sram@fff80000 {
+ compatible = "hisilicon,hi6220-sramctrl", "syscon";
+ reg = <0x0 0xfff80000 0x0 0x12000>;
+ };
+
ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
@@ -147,12 +258,14 @@
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
media_ctrl: media_ctrl@f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0x0 0xf4410000 0x0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
pm_ctrl: pm_ctrl@f7032000 {
@@ -161,6 +274,19 @@
#clock-cells = <1>;
};
+ stub_clock: stub_clock {
+ compatible = "hisilicon,hi6220-stub-clk";
+ hisilicon,hi6220-clk-sram = <&sram>;
+ #clock-cells = <1>;
+ mbox-names = "mbox-tx";
+ mboxes = <&mailbox 1 0 11>;
+ };
+
+ medianoc_ade: medianoc_ade@f4520000 {
+ compatible = "syscon";
+ reg = <0x0 0xf4520000 0x0 0x4000>;
+ };
+
uart0: uart@f8015000 { /* console */
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf8015000 0x0 0x1000>;
@@ -177,6 +303,8 @@
clocks = <&sys_ctrl HI6220_UART1_PCLK>,
<&sys_ctrl HI6220_UART1_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
status = "disabled";
};
@@ -187,6 +315,8 @@
clocks = <&sys_ctrl HI6220_UART2_PCLK>,
<&sys_ctrl HI6220_UART2_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
status = "disabled";
};
@@ -197,6 +327,9 @@
clocks = <&sys_ctrl HI6220_UART3_PCLK>,
<&sys_ctrl HI6220_UART3_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+ status = "disabled";
};
uart4: uart@f7114000 {
@@ -206,7 +339,694 @@
clocks = <&sys_ctrl HI6220_UART4_PCLK>,
<&sys_ctrl HI6220_UART4_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
status = "disabled";
};
+
+ dma0: dma@f7370000 {
+ compatible = "hisilicon,k3-dma-1.0";
+ reg = <0x0 0xf7370000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ dma-requests = <32>;
+ interrupts = <0 84 4>;
+ clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
+ dma-no-cci;
+ dma-type = "hi6220_dma";
+ status = "ok";
+ };
+
+ dual_timer0: dual_timer@f8008000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xf8008000 0x0 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ao_ctrl 27>;
+ clock-names = "apb_pclk";
+ };
+
+ rtc0: rtc@170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0xf8003000 0x0 0x1000>;
+ interrupts = <0 12 4>;
+ clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
+ clock-names = "apb_pclk";
+ };
+
+ pmx0: pinmux@f7010000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xf7010000 0x0 0x27c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+ pinctrl-single,gpio-range = <
+ &range 80 8 MUX_M0 /* gpio 3: [0..7] */
+ &range 88 8 MUX_M0 /* gpio 4: [0..7] */
+ &range 96 8 MUX_M0 /* gpio 5: [0..7] */
+ &range 104 8 MUX_M0 /* gpio 6: [0..7] */
+ &range 112 8 MUX_M0 /* gpio 7: [0..7] */
+ &range 120 2 MUX_M0 /* gpio 8: [0..1] */
+ &range 2 6 MUX_M1 /* gpio 8: [2..7] */
+ &range 8 8 MUX_M1 /* gpio 9: [0..7] */
+ &range 0 1 MUX_M1 /* gpio 10: [0] */
+ &range 16 7 MUX_M1 /* gpio 10: [1..7] */
+ &range 23 3 MUX_M1 /* gpio 11: [0..2] */
+ &range 28 5 MUX_M1 /* gpio 11: [3..7] */
+ &range 33 3 MUX_M1 /* gpio 12: [0..2] */
+ &range 43 5 MUX_M1 /* gpio 12: [3..7] */
+ &range 48 8 MUX_M1 /* gpio 13: [0..7] */
+ &range 56 8 MUX_M1 /* gpio 14: [0..7] */
+ &range 74 6 MUX_M1 /* gpio 15: [0..5] */
+ &range 122 1 MUX_M1 /* gpio 15: [6] */
+ &range 126 1 MUX_M1 /* gpio 15: [7] */
+ &range 127 8 MUX_M1 /* gpio 16: [0..7] */
+ &range 135 8 MUX_M1 /* gpio 17: [0..7] */
+ &range 143 8 MUX_M1 /* gpio 18: [0..7] */
+ &range 151 8 MUX_M1 /* gpio 19: [0..7] */
+ >;
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ pmx1: pinmux@f7010800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xf7010800 0x0 0x28c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ };
+
+ pmx2: pinmux@f8001800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xf8001800 0x0 0x78>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ };
+
+ gpio0: gpio@f8011000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8011000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio1: gpio@f8012000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8012000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio2: gpio@f8013000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8013000 0x0 0x1000>;
+ interrupts = <0 54 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio3: gpio@f8014000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8014000 0x0 0x1000>;
+ interrupts = <0 55 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 80 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio4: gpio@f7020000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7020000 0x0 0x1000>;
+ interrupts = <0 56 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 88 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio5: gpio@f7021000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7021000 0x0 0x1000>;
+ interrupts = <0 57 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 96 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio6: gpio@f7022000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7022000 0x0 0x1000>;
+ interrupts = <0 58 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 104 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio7: gpio@f7023000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7023000 0x0 0x1000>;
+ interrupts = <0 59 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 112 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio8: gpio@f7024000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7024000 0x0 0x1000>;
+ interrupts = <0 60 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio9: gpio@f7025000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7025000 0x0 0x1000>;
+ interrupts = <0 61 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 8 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio10: gpio@f7026000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7026000 0x0 0x1000>;
+ interrupts = <0 62 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio11: gpio@f7027000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7027000 0x0 0x1000>;
+ interrupts = <0 63 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio12: gpio@f7028000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7028000 0x0 0x1000>;
+ interrupts = <0 64 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio13: gpio@f7029000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7029000 0x0 0x1000>;
+ interrupts = <0 65 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 48 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio14: gpio@f702a000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702a000 0x0 0x1000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 56 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio15: gpio@f702b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702b000 0x0 0x1000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <
+ &pmx0 0 74 6
+ &pmx0 6 122 1
+ &pmx0 7 126 1
+ >;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio16: gpio@f702c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702c000 0x0 0x1000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 127 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio17: gpio@f702d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702d000 0x0 0x1000>;
+ interrupts = <0 69 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 135 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio18: gpio@f702e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702e000 0x0 0x1000>;
+ interrupts = <0 70 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 143 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio19: gpio@f702f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702f000 0x0 0x1000>;
+ interrupts = <0 71 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 151 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ spi0: spi@f7106000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xf7106000 0x0 0x1000>;
+ interrupts = <0 50 4>;
+ bus-id = <0>;
+ enable-dma = <0>;
+ clocks = <&sys_ctrl HI6220_SPI_CLK>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio6 2 0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@f7100000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7100000 0x0 0x1000>;
+ interrupts = <0 44 4>;
+ clocks = <&sys_ctrl HI6220_I2C0_CLK>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@f7101000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7101000 0x0 0x1000>;
+ clocks = <&sys_ctrl HI6220_I2C1_CLK>;
+ interrupts = <0 45 4>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@f7102000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7102000 0x0 0x1000>;
+ clocks = <&sys_ctrl HI6220_I2C2_CLK>;
+ interrupts = <0 46 4>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
+ status = "disabled";
+ };
+
+ fixed_5v_hub: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed_5v_hub";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio0 7 0>;
+ regulator-always-on;
+ };
+
+ usb_phy: usbphy {
+ compatible = "hisilicon,hi6220-usb-phy";
+ #phy-cells = <0>;
+ phy-supply = <&fixed_5v_hub>;
+ hisilicon,peripheral-syscon = <&sys_ctrl>;
+ };
+
+ usb: usb@f72c0000 {
+ compatible = "hisilicon,hi6220-usb";
+ reg = <0x0 0xf72c0000 0x0 0x40000>;
+ phys = <&usb_phy>;
+ phy-names = "usb2-phy";
+ clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-use-dma;
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 128 128 128 128>;
+ interrupts = <0 77 0x4>;
+ };
+
+ mailbox: mailbox@f7510000 {
+ compatible = "hisilicon,hi6220-mbox";
+ reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
+ <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <3>;
+ };
+
+ dwmmc_0: dwmmc0@f723d000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ num-slots = <0x1>;
+ cap-mmc-highspeed;
+ non-removable;
+ reg = <0x0 0xf723d000 0x0 0x1000>;
+ interrupts = <0x0 0x48 0x4>;
+ clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
+ clock-names = "ciu", "biu";
+ resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
+ bus-width = <0x8>;
+ vmmc-supply = <&ldo19>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
+ &emmc_cfg_func &emmc_rst_cfg_func>;
+ };
+
+ dwmmc_1: dwmmc1@f723e000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ num-slots = <0x1>;
+ card-detect-delay = <200>;
+ hisilicon,peripheral-syscon = <&ao_ctrl>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ reg = <0x0 0xf723e000 0x0 0x1000>;
+ interrupts = <0x0 0x49 0x4>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
+ clock-names = "ciu", "biu";
+ resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
+ vqmmc-supply = <&ldo7>;
+ vmmc-supply = <&ldo10>;
+ bus-width = <0x4>;
+ disable-wp;
+ cd-gpios = <&gpio1 0 1>;
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
+ pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
+ };
+
+ dwmmc_2: dwmmc2@f723f000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ status = "okay";
+ num-slots = <0x1>;
+ reg = <0x0 0xf723f000 0x0 0x1000>;
+ interrupts = <0x0 0x4a 0x4>;
+ clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
+ clock-names = "ciu", "biu";
+ resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
+ bus-width = <0x4>;
+ broken-cd;
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
+ pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
+ };
+
+ tsensor: tsensor@0,f7030700 {
+ compatible = "hisilicon,tsensor";
+ reg = <0x0 0xf7030700 0x0 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_ctrl 22>;
+ clock-names = "thermal_clk";
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+
+ cls0: cls0 {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ sustainable-power = <3326>;
+
+ /* sensor ID */
+ thermal-sensors = <&tsensor 2>;
+
+ trips {
+ threshold: trip-point@0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ target: trip-point@1 {
+ temperature = <75000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ contribution = <1024>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ mtcmos {
+ compatible = "hisilicon,hi6220-mtcmos-driver";
+ hisilicon,mtcmos-steady-us = <10>;
+ hisilicon,mtcmos-sc-on-base = <0xf7800000>;
+ hisilicon,mtcmos-acpu-on-base = <0xf65a0000>;
+
+ g3d_vdd: regulator@a1{
+ regulator-name = "G3D_PD_VDD";
+ regulator-compatible = "mtcmos1";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <1 0x1>;
+ };
+
+ soc_med: regulator@a2{
+ regulator-name = "SOC_MED";
+ regulator-compatible = "mtcmos2";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <2 0x1>;
+ };
+ };
+
+ ade: ade@f4100000 {
+ compatible = "hisilicon,hi6220-ade";
+ reg = <0x0 0xf4100000 0x0 0x7800>;
+ reg-names = "ade_base";
+ hisilicon,noc-syscon = <&medianoc_ade>;
+ resets = <&media_ctrl MEDIA_ADE>;
+ interrupts = <0 115 4>; /* ldi interrupt */
+
+ clocks = <&media_ctrl HI6220_ADE_CORE>,
+ <&media_ctrl HI6220_CODEC_JPEG>,
+ <&media_ctrl HI6220_ADE_PIX_SRC>;
+ /*clock name*/
+ clock-names = "clk_ade_core",
+ "clk_codec_jpeg",
+ "clk_ade_pix";
+
+ assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
+ <&media_ctrl HI6220_CODEC_JPEG>;
+ assigned-clock-rates = <360000000>, <288000000>;
+ status = "disabled";
+
+ port {
+ ade_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+
+ dsi: dsi@f4107800 {
+ compatible = "hisilicon,hi6220-dsi";
+ reg = <0x0 0xf4107800 0x0 0x100>;
+ clocks = <&media_ctrl HI6220_DSI_PCLK>;
+ clock-names = "pclk";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 0 for input port */
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ade_out>;
+ };
+ };
+ };
+ };
+
+ mali:mali@f4080000 {
+ compatible = "arm,mali-450", "arm,mali-utgard";
+ reg = <0x0 0x3f100000 0x0 0x00708000>;
+ clocks = <&media_ctrl HI6220_G3D_CLK>,
+ <&media_ctrl HI6220_G3D_PCLK>;
+ clock-names = "clk_g3d", "pclk_g3d";
+ G3D_PD_VDD-supply = <&g3d_vdd>;
+ mali_def_freq = <500>;
+ pclk_freq = <144>;
+ dfs_steps = <2>;
+ dfs_lockprf = <1>;
+ dfs_limit_max_prf = <1>;
+ dfs_profile_num = <2>;
+ dfs_profiles = <250 3 0>, <500 1 0>;
+ mali_type = <2>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <1 126 4>, /*gp*/
+ <1 126 4>, /*gp mmu*/
+ <1 126 4>, /*pp bc*/
+ <1 126 4>, /*pmu*/
+ <1 126 4>, /*pp0*/
+ <1 126 4>,
+ <1 126 4>, /*pp1*/
+ <1 126 4>,
+ <1 126 4>, /*pp2*/
+ <1 126 4>,
+ <1 126 4>, /*pp4*/
+ <1 126 4>,
+ <1 126 4>, /*pp5*/
+ <1 126 4>,
+ <1 126 4>, /*pp6*/
+ <1 126 4>;
+ interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU",
+ "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1",
+ "IRQPP2", "IRQPPMMU2","IRQPP4", "IRQPPMMU4",
+ "IRQPP5", "IRQPPMMU5", "IRQPP6", "IRQPPMMU6";
+ };
+
+ i2s0: hi6210_i2s {
+ compatible = "hisilicon,hi6210-i2s";
+ reg = <0x0 0xf7118000 0x0 0x8000>, /* i2s unit */
+ <0x0 0xf7030000 0x0 0x400>, /* syscon */
+ <0x0 0xf7032000 0x0 0x400>; /* pmctrl */
+ interrupts = <0 123 0x4>; /* 155 "DigACodec_intr" - 32 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pmx_func &bt_cfg_func>;
+ clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
+ <&sys_ctrl HI6220_BBPPLL0_DIV>;
+ clock-names = "dacodec", "i2s-base";
+ dmas = <&dma0 15 &dma0 14>;
+ dma-names = "rx", "tx";
+ };
+
+ hi6210_hdmi_card: hi6210_hdmi_card {
+ compatible = "hisilicon,hi6210-hdmi-audio-card";
+ reg = <0 0 0 0>;
+ sound-dai = <&i2s0>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
new file mode 100644
index 000000000000..d103cf10f0fa
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
@@ -0,0 +1,727 @@
+/*
+ * pinctrl dts fils for Hislicon HiKey development board
+ *
+ */
+#include <dt-bindings/pinctrl/hisi.h>
+
+/ {
+ soc {
+ pmx0: pinmux@f7010000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &boot_sel_pmx_func
+ &hkadc_ssi_pmx_func
+ &codec_clk_pmx_func
+ &pwm_in_pmx_func
+ &bl_pwm_pmx_func
+ >;
+
+ boot_sel_pmx_func: boot_sel_pmx_func {
+ pinctrl-single,pins = <
+ 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
+ >;
+ };
+
+ emmc_pmx_func: emmc_pmx_func {
+ pinctrl-single,pins = <
+ 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
+ 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
+ 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
+ 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
+ 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
+ 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
+ 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
+ 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
+ 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
+ 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
+ >;
+ };
+
+ sd_pmx_func: sd_pmx_func {
+ pinctrl-single,pins = <
+ 0xc MUX_M0 /* SD_CLK (IOMG003) */
+ 0x10 MUX_M0 /* SD_CMD (IOMG004) */
+ 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
+ 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
+ 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
+ 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
+ >;
+ };
+ sd_pmx_idle: sd_pmx_idle {
+ pinctrl-single,pins = <
+ 0xc MUX_M1 /* SD_CLK (IOMG003) */
+ 0x10 MUX_M1 /* SD_CMD (IOMG004) */
+ 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
+ 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
+ 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
+ 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
+ >;
+ };
+
+ sdio_pmx_func: sdio_pmx_func {
+ pinctrl-single,pins = <
+ 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
+ 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
+ 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
+ 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
+ 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
+ 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
+ >;
+ };
+ sdio_pmx_idle: sdio_pmx_idle {
+ pinctrl-single,pins = <
+ 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
+ 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
+ 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
+ 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
+ 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
+ 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
+ >;
+ };
+
+ isp_pmx_func: isp_pmx_func {
+ pinctrl-single,pins = <
+ 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
+ 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
+ 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
+ 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
+ 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
+ 0x38 MUX_M1 /* ISP_PWM (IOMG014) */
+ 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
+ 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
+ 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
+ 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
+ 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
+ 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
+ 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
+ 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
+ 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
+ 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
+ >;
+ };
+
+ hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
+ pinctrl-single,pins = <
+ 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
+ >;
+ };
+
+ codec_clk_pmx_func: codec_clk_pmx_func {
+ pinctrl-single,pins = <
+ 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
+ >;
+ };
+
+ codec_pmx_func: codec_pmx_func {
+ pinctrl-single,pins = <
+ 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
+ 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
+ 0x78 MUX_M0 /* CODEC_DI (IOMG030) */
+ 0x7c MUX_M0 /* CODEC_DO (IOMG031) */
+ >;
+ };
+
+ fm_pmx_func: fm_pmx_func {
+ pinctrl-single,pins = <
+ 0x80 MUX_M1 /* FM_XCLK (IOMG032) */
+ 0x84 MUX_M1 /* FM_XFS (IOMG033) */
+ 0x88 MUX_M1 /* FM_DI (IOMG034) */
+ 0x8c MUX_M1 /* FM_DO (IOMG035) */
+ >;
+ };
+
+ bt_pmx_func: bt_pmx_func {
+ pinctrl-single,pins = <
+ 0x90 MUX_M0 /* BT_XCLK (IOMG036) */
+ 0x94 MUX_M0 /* BT_XFS (IOMG037) */
+ 0x98 MUX_M0 /* BT_DI (IOMG038) */
+ 0x9c MUX_M0 /* BT_DO (IOMG039) */
+ >;
+ };
+
+ pwm_in_pmx_func: pwm_in_pmx_func {
+ pinctrl-single,pins = <
+ 0xb8 MUX_M1 /* PWM_IN (IOMG046) */
+ >;
+ };
+
+ bl_pwm_pmx_func: bl_pwm_pmx_func {
+ pinctrl-single,pins = <
+ 0xbc MUX_M1 /* BL_PWM (IOMG047) */
+ >;
+ };
+
+ uart0_pmx_func: uart0_pmx_func {
+ pinctrl-single,pins = <
+ 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
+ 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
+ >;
+ };
+
+ uart1_pmx_func: uart1_pmx_func {
+ pinctrl-single,pins = <
+ 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
+ 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
+ 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
+ 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
+ >;
+ };
+
+ uart2_pmx_func: uart2_pmx_func {
+ pinctrl-single,pins = <
+ 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
+ 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
+ 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
+ 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
+ >;
+ };
+
+ uart3_pmx_func: uart3_pmx_func {
+ pinctrl-single,pins = <
+ 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
+ 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
+ 0x188 MUX_M1 /* UART3_RXD (IOMG098) */
+ 0x18c MUX_M1 /* UART3_TXD (IOMG099) */
+ >;
+ };
+
+ uart4_pmx_func: uart4_pmx_func {
+ pinctrl-single,pins = <
+ 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
+ 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
+ 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
+ 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
+ >;
+ };
+
+ uart5_pmx_func: uart5_pmx_func {
+ pinctrl-single,pins = <
+ 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
+ 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
+ >;
+ };
+
+ i2c0_pmx_func: i2c0_pmx_func {
+ pinctrl-single,pins = <
+ 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
+ 0xec MUX_M0 /* I2C0_SDA (IOMG059) */
+ >;
+ };
+
+ i2c1_pmx_func: i2c1_pmx_func {
+ pinctrl-single,pins = <
+ 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
+ 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
+ >;
+ };
+
+ i2c2_pmx_func: i2c2_pmx_func {
+ pinctrl-single,pins = <
+ 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
+ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
+ >;
+ };
+
+ spi0_pmx_func: spi0_pmx_func {
+ pinctrl-single,pins = <
+ 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
+ 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
+ 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */
+ 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */
+ >;
+ };
+
+ modem_pcm_pmx_func: modem_pcm_pmx_func {
+ pinctrl-single,pins = <
+ 0x198 MUX_M3 /* MODEM_PCM_XCLK (IOMG102) */
+ 0x19c MUX_M3 /* MODEM_PCM_XFS (IOMG103) */
+ 0x1d0 MUX_M3 /* MODEM_PCM_DI (IOMG116) */
+ 0x1d4 MUX_M3 /* MODEM_PCM_DO (IOMG117) */
+ >;
+ };
+
+ };
+
+ pmx1: pinmux@f7010800 {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &boot_sel_cfg_func
+ &hkadc_ssi_cfg_func
+ &codec_clk_cfg_func
+ &pwm_in_cfg_func
+ &bl_pwm_cfg_func
+ >;
+
+ boot_sel_cfg_func: boot_sel_cfg_func {
+ pinctrl-single,pins = <
+ 0x0 0x0 /* BOOT_SEL (IOCFG000) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
+ pinctrl-single,pins = <
+ 0x6c 0x0 /* HKADC_SSI (IOCFG027) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ emmc_clk_cfg_func: emmc_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x104 0x0 /* EMMC_CLK (IOCFG065) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+
+ emmc_cfg_func: emmc_cfg_func {
+ pinctrl-single,pins = <
+ 0x108 0x0 /* EMMC_CMD (IOCFG066) */
+ 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
+ 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
+ 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
+ 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
+ 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
+ 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
+ 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
+ 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+
+ emmc_rst_cfg_func: emmc_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+
+ sd_clk_cfg_func: sd_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0xc 0x0 /* SD_CLK (IOCFG003) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
+ };
+ sd_clk_cfg_idle: sd_clk_cfg_idle {
+ pinctrl-single,pins = <
+ 0xc 0x0 /* SD_CLK (IOCFG003) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sd_cfg_func: sd_cfg_func {
+ pinctrl-single,pins = <
+ 0x10 0x0 /* SD_CMD (IOCFG004) */
+ 0x14 0x0 /* SD_DATA0 (IOCFG005) */
+ 0x18 0x0 /* SD_DATA1 (IOCFG006) */
+ 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
+ 0x20 0x0 /* SD_DATA3 (IOCFG008) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+ sd_cfg_idle: sd_cfg_idle {
+ pinctrl-single,pins = <
+ 0x10 0x0 /* SD_CMD (IOCFG004) */
+ 0x14 0x0 /* SD_DATA0 (IOCFG005) */
+ 0x18 0x0 /* SD_DATA1 (IOCFG006) */
+ 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
+ 0x20 0x0 /* SD_DATA3 (IOCFG008) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sdio_clk_cfg_func: sdio_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x134 0x0 /* SDIO_CLK (IOCFG077) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+ sdio_clk_cfg_idle: sdio_clk_cfg_idle {
+ pinctrl-single,pins = <
+ 0x134 0x0 /* SDIO_CLK (IOCFG077) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sdio_cfg_func: sdio_cfg_func {
+ pinctrl-single,pins = <
+ 0x138 0x0 /* SDIO_CMD (IOCFG078) */
+ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
+ 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
+ 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
+ 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+ sdio_cfg_idle: sdio_cfg_idle {
+ pinctrl-single,pins = <
+ 0x138 0x0 /* SDIO_CMD (IOCFG078) */
+ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
+ 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
+ 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
+ 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ isp_cfg_func1: isp_cfg_func1 {
+ pinctrl-single,pins = <
+ 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
+ 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
+ 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
+ 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
+ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
+ 0x3c 0x0 /* ISP_PWM (IOCFG015) */
+ 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
+ 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
+ 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
+ 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
+ 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
+ 0x58 0x0 /* ISP_SDA0 (IOCFG022) */
+ 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
+ 0x60 0x0 /* ISP_SDA1 (IOCFG024) */
+ 0x64 0x0 /* ISP_SCL1 (IOCFG025) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ isp_cfg_idle1: isp_cfg_idle1 {
+ pinctrl-single,pins = <
+ 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
+ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ isp_cfg_func2: isp_cfg_func2 {
+ pinctrl-single,pins = <
+ 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ codec_clk_cfg_func: codec_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x70 0x0 /* CODEC_CLK (IOCFG028) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+ codec_clk_cfg_idle: codec_clk_cfg_idle {
+ pinctrl-single,pins = <
+ 0x70 0x0 /* CODEC_CLK (IOCFG028) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ codec_cfg_func1: codec_cfg_func1 {
+ pinctrl-single,pins = <
+ 0x74 0x0 /* DMIC_CLK (IOCFG029) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ codec_cfg_func2: codec_cfg_func2 {
+ pinctrl-single,pins = <
+ 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
+ 0x7c 0x0 /* CODEC_DI (IOCFG031) */
+ 0x80 0x0 /* CODEC_DO (IOCFG032) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+ codec_cfg_idle2: codec_cfg_idle2 {
+ pinctrl-single,pins = <
+ 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
+ 0x7c 0x0 /* CODEC_DI (IOCFG031) */
+ 0x80 0x0 /* CODEC_DO (IOCFG032) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ fm_cfg_func: fm_cfg_func {
+ pinctrl-single,pins = <
+ 0x84 0x0 /* FM_XCLK (IOCFG033) */
+ 0x88 0x0 /* FM_XFS (IOCFG034) */
+ 0x8c 0x0 /* FM_DI (IOCFG035) */
+ 0x90 0x0 /* FM_DO (IOCFG036) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ bt_cfg_func: bt_cfg_func {
+ pinctrl-single,pins = <
+ 0x94 0x0 /* BT_XCLK (IOCFG037) */
+ 0x98 0x0 /* BT_XFS (IOCFG038) */
+ 0x9c 0x0 /* BT_DI (IOCFG039) */
+ 0xa0 0x0 /* BT_DO (IOCFG040) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ bt_cfg_idle: bt_cfg_idle {
+ pinctrl-single,pins = <
+ 0x94 0x0 /* BT_XCLK (IOCFG037) */
+ 0x98 0x0 /* BT_XFS (IOCFG038) */
+ 0x9c 0x0 /* BT_DI (IOCFG039) */
+ 0xa0 0x0 /* BT_DO (IOCFG040) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ pwm_in_cfg_func: pwm_in_cfg_func {
+ pinctrl-single,pins = <
+ 0xbc 0x0 /* PWM_IN (IOCFG047) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ bl_pwm_cfg_func: bl_pwm_cfg_func {
+ pinctrl-single,pins = <
+ 0xc0 0x0 /* BL_PWM (IOCFG048) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart0_cfg_func1: uart0_cfg_func1 {
+ pinctrl-single,pins = <
+ 0xc4 0x0 /* UART0_RXD (IOCFG049) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart0_cfg_func2: uart0_cfg_func2 {
+ pinctrl-single,pins = <
+ 0xc8 0x0 /* UART0_TXD (IOCFG050) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+
+ uart1_cfg_func1: uart1_cfg_func1 {
+ pinctrl-single,pins = <
+ 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
+ 0xd4 0x0 /* UART1_RXD (IOCFG053) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart1_cfg_func2: uart1_cfg_func2 {
+ pinctrl-single,pins = <
+ 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
+ 0xd8 0x0 /* UART1_TXD (IOCFG054) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart2_cfg_func: uart2_cfg_func {
+ pinctrl-single,pins = <
+ 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
+ 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
+ 0xe4 0x0 /* UART2_RXD (IOCFG057) */
+ 0xe8 0x0 /* UART2_TXD (IOCFG058) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart3_cfg_func: uart3_cfg_func {
+ pinctrl-single,pins = <
+ 0x190 0x0 /* UART3_CTS_N (IOCFG100) */
+ 0x194 0x0 /* UART3_RTS_N (IOCFG101) */
+ 0x198 0x0 /* UART3_RXD (IOCFG102) */
+ 0x19c 0x0 /* UART3_TXD (IOCFG103) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart4_cfg_func: uart4_cfg_func {
+ pinctrl-single,pins = <
+ 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
+ 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
+ 0x1e8 0x0 /* UART4_RXD (IOCFG122) */
+ 0x1ec 0x0 /* UART4_TXD (IOCFG123) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart5_cfg_func: uart5_cfg_func {
+ pinctrl-single,pins = <
+ 0x1d8 0x0 /* UART4_RXD (IOCFG118) */
+ 0x1dc 0x0 /* UART4_TXD (IOCFG119) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ i2c0_cfg_func: i2c0_cfg_func {
+ pinctrl-single,pins = <
+ 0xec 0x0 /* I2C0_SCL (IOCFG059) */
+ 0xf0 0x0 /* I2C0_SDA (IOCFG060) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ i2c1_cfg_func: i2c1_cfg_func {
+ pinctrl-single,pins = <
+ 0xf4 0x0 /* I2C1_SCL (IOCFG061) */
+ 0xf8 0x0 /* I2C1_SDA (IOCFG062) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ i2c2_cfg_func: i2c2_cfg_func {
+ pinctrl-single,pins = <
+ 0xfc 0x0 /* I2C2_SCL (IOCFG063) */
+ 0x100 0x0 /* I2C2_SDA (IOCFG064) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ spi0_cfg_func: spi0_cfg_func {
+ pinctrl-single,pins = <
+ 0x1b0 0x0 /* SPI0_DI (IOCFG108) */
+ 0x1b4 0x0 /* SPI0_DO (IOCFG109) */
+ 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */
+ 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ modem_pcm_cfg_func: modem_pcm_cfg_func {
+ pinctrl-single,pins = <
+ 0x1a8 0x0 /* MODEM_PCM_XCLK (IOCFG106) */
+ 0x1ac 0x0 /* MODEM_PCM_XFS (IOCFG107) */
+ 0x1e0 0x0 /* MODEM_PCM_DI (IOCFG120) */
+ 0x1e4 0x0 /* MODEM_PCM_DO (IOCFG121) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE2_02MA DRIVE_MASK>;
+ };
+ };
+
+ pmx2: pinmux@f8001800 {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &rstout_n_cfg_func
+ >;
+
+ rstout_n_cfg_func: rstout_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x0 0x0 /* RSTOUT_N (IOCFG000) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
+ pinctrl-single,pins = <
+ 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sysclk0_en_cfg_func: sysclk0_en_cfg_func {
+ pinctrl-single,pins = <
+ 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ jtag_tdo_cfg_func: jtag_tdo_cfg_func {
+ pinctrl-single,pins = <
+ 0xc 0x0 /* JTAG_TDO (IOCFG003) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+
+ rf_reset_cfg_func: rf_reset_cfg_func {
+ pinctrl-single,pins = <
+ 0x70 0x0 /* RF_RESET0 (IOCFG028) */
+ 0x74 0x0 /* RF_RESET1 (IOCFG029) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
new file mode 100755
index 000000000000..38f1ea879ea1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for hisilicon pinctrl bindings.
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_HISI_H
+#define _DT_BINDINGS_PINCTRL_HISI_H
+
+/* iomg bit definition */
+#define MUX_M0 0
+#define MUX_M1 1
+#define MUX_M2 2
+#define MUX_M3 3
+#define MUX_M4 4
+#define MUX_M5 5
+#define MUX_M6 6
+#define MUX_M7 7
+
+/* iocg bit definition */
+#define PULL_MASK (3)
+#define PULL_DIS (0)
+#define PULL_UP (1 << 0)
+#define PULL_DOWN (1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK (7 << 4)
+#define DRIVE1_02MA (0 << 4)
+#define DRIVE1_04MA (1 << 4)
+#define DRIVE1_08MA (2 << 4)
+#define DRIVE1_10MA (3 << 4)
+#define DRIVE2_02MA (0 << 4)
+#define DRIVE2_04MA (1 << 4)
+#define DRIVE2_08MA (2 << 4)
+#define DRIVE2_10MA (3 << 4)
+#define DRIVE3_04MA (0 << 4)
+#define DRIVE3_08MA (1 << 4)
+#define DRIVE3_12MA (2 << 4)
+#define DRIVE3_16MA (3 << 4)
+#define DRIVE3_20MA (4 << 4)
+#define DRIVE3_24MA (5 << 4)
+#define DRIVE3_32MA (6 << 4)
+#define DRIVE3_40MA (7 << 4)
+#define DRIVE4_02MA (0 << 4)
+#define DRIVE4_04MA (2 << 4)
+#define DRIVE4_08MA (4 << 4)
+#define DRIVE4_10MA (6 << 4)
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 13:13:40 +0000