diff options
| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2013-12-01 23:13:56 -0500 |
|---|---|---|
| committer | Carl Worth <cworth@cworth.org> | 2013-12-12 15:40:48 -0800 |
| commit | bd304ffc859534e8d899c19e98a06caa762f8589 (patch) | |
| tree | 64ffa79b6e07be60abf6ead462fffb2c46227ddf | |
| parent | 16c5f241411798ac4360ff8c3500c1d68c8a6127 (diff) | |
nv50: Fix GPU_READING/WRITING bit removal
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
CC: "9.1, 9.2, 10.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c45cf6199fc493538cef33125c8a97a892e2ca83)
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_state_validate.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_tex.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c index f5e7b36809..9a4c5ea0c0 100644 --- a/src/gallium/drivers/nv50/nv50_state_validate.c +++ b/src/gallium/drivers/nv50/nv50_state_validate.c @@ -61,7 +61,7 @@ nv50_validate_fb(struct nv50_context *nv50) if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) nv50->state.rt_serialize = TRUE; mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; - mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING; + mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; /* only register for writing, otherwise we'd always serialize here */ BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR); @@ -91,7 +91,7 @@ nv50_validate_fb(struct nv50_context *nv50) if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) nv50->state.rt_serialize = TRUE; mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; - mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING; + mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR); } else { diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c index 48b35d703b..328a204ac6 100644 --- a/src/gallium/drivers/nv50/nv50_tex.c +++ b/src/gallium/drivers/nv50/nv50_tex.c @@ -271,7 +271,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s) nv50->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32); - res->status &= NOUVEAU_BUFFER_STATUS_GPU_WRITING; + res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING; BCTX_REFN(nv50->bufctx_3d, TEXTURES, res, RD); |