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/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/armv8/mmu.h>
/*************************************************************************
*
* Startup Code (reset vector)
*
*************************************************************************/
.globl _start
_start:
b reset
.align 3
.globl _TEXT_BASE
_TEXT_BASE:
.quad CONFIG_SYS_TEXT_BASE
/*
* These are defined in the linker script.
*/
.globl _end_ofs
_end_ofs:
.quad _end - _start
.globl _bss_start_ofs
_bss_start_ofs:
.quad __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.quad __bss_end - _start
.macro _mov_imm16 _reg, _val, _shift
.if (\_val >> \_shift) & 0xffff
.if (\_val & (1 << \_shift - 1))
movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
.else
mov \_reg, \_val & (0xffff << \_shift)
.endif
.endif
.endm
.macro mov_imm _reg, _val
.if (\_val) == 0
mov \_reg, #0
.else
_mov_imm16 \_reg, (\_val), 0
_mov_imm16 \_reg, (\_val), 16
_mov_imm16 \_reg, (\_val), 32
_mov_imm16 \_reg, (\_val), 48
.endif
.endm
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define uartbase 0x1c090000 /* FPGA UART0 */
#define uartclk 24000000
#endif
//#define uartbase 0x1c0a0000 /* FPGA UART1 */
//#define uartclk 24000000
//#define uartbase 0x1c0b0000 /* FPGA UART2 */
//#define uartclk 24000000
//#define uartbase 0x1c0c0000 /* FPGA UART3 */
//#define uartclk 24000000
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define uartbase 0x7ff80000 /* SoC UART0 */
#define uartclk 7273800
#endif
//#define uartclk 100000000?
//#define uartbase 0x7ff70000 /* SoC UART 1 */
//#define uartclk 7273800
//#define uartclk 24000000
init_pl011:
mov_imm x3, uartbase
mov_imm w1, uartclk
mov_imm w2, 115200
lsl w1, w1, #2
udiv w2, w1, w2
lsr w1, w2, #6
str w1, [x3, #0x24]
and w1, w2, #0x3f
str w1, [x3, #0x28]
mov w1, #(1 << 4 | 3 << 5)
str w1, [x3, #0x2c]
str wzr, [x3, #0x004]
mov w1, #(1 << 9 | 1 << 8 | 1 << 0)
str w1, [x3, #0x30]
ret
ENTRY(printascii)
mov_imm x3, uartbase
1: ldrb w0, [x2], #1
cbz w0, 4f
2: ldr w1, [x3, #0x18]
tbnz w1, #5, 2b
str w0, [x3, #0x00]
3: ldr w1, [x3, #0x18]
tbnz w1, #3, 3b
b 1b
4: ret
ENDPROC(printascii)
/* END TEST */
reset_str:
.asciz "reset\r\n"
lowlevel_str:
.asciz "lowlevel init\r\n"
master_str:
.asciz "MASTER CPU\r\n"
slave_str:
.asciz "SLAVE CPU\r\n"
gic1master_str:
.asciz "GIC 1 master CPU init\r\n"
gic1slave_str:
.asciz "GIC 1 slave CPU init\r\n"
gic2_str:
.asciz "GIC 2 init\r\n"
slave_wait_str:
.asciz "SLAVE wait for master CPU\r\n"
main_str:
.asciz "jump to _main\r\n"
.align 3
reset:
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
*/
bl init_pl011
adr x2, reset_str
bl printascii
adr x0, vectors
switch_el x1, 3f, 2f, 1f
3: msr vbar_el3, x0
mrs x0, scr_el3
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
b 0f
2: msr vbar_el2, x0
mov x0, #0x33ff
msr cptr_el2, x0 /* Enable FP/SIMD */
b 0f
1: msr vbar_el1, x0
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
/*
* Cache/BPB/TLB Invalidate
* i-cache is invalidated before enabled in icache_enable()
* tlb is invalidated before mmu is enabled in dcache_enable()
* d-cache is invalidated before enabled in dcache_enable()
*/
/* Processor specific initialization */
bl lowlevel_init
branch_if_master x0, x1, master_cpu
/*
* Slave CPUs
*/
slave_cpu:
wfe
ldr x1, =CPU_RELEASE_ADDR
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
/*
* Master CPU
*/
master_cpu:
bl _main
/*-----------------------------------------------------------------------*/
WEAK(lowlevel_init)
mov x29, lr /* Save LR */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl gic_init_secure
1:
mov x28, x0
adr x2, gic2_str
bl printascii
mov x0, x28
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
#endif
branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All slaves will enter EL2 and optionally EL1.
*/
bl armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl armv8_switch_to_el1
#endif
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
WEAK(smp_kick_all_cpus)
/* Kick secondary cpus up by SGI 0 interrupt */
mov x29, lr /* Save LR */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
ldr x0, =GICD_BASE
bl gic_kick_secondary_cpus
#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(smp_kick_all_cpus)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
3: msr vbar_el3, x0
b 0f
2: msr vbar_el2, x0
b 0f
1: msr vbar_el1, x0
0:
ret
ENDPROC(c_runtime_cpu_setup)
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