feat(sys_reg_trace): add trace system registers access test

Added a test to read trace system registers to ensure that EL3
is giving permission to non-secure EL2 to access these registers.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I0bdbb5aff81a78fc3a3766278c48b25bb6e1779f

11 files changed, 164 insertions, 0 deletions

diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index a6f3768..332f1d8 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -263,6 +263,15 @@ typedef test_result_t (*test_function_arg_t)(void *arg);
 		}								\
 	} while (false)
 
+#define SKIP_TEST_IF_SYS_REG_TRACE_NOT_SUPPORTED()				\
+	do {									\
+		if (!get_armv8_0_sys_reg_trace_support()) {			\
+			tftf_testcase_printf("ARMv8-system register"		\
+					     "trace not supported\n");		\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
 /* Helper macro to verify if system suspend API is supported */
 #define is_psci_sys_susp_supported()	\
 		(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND)		\
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index 3ecc047..a4b7d7d 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -104,6 +104,11 @@
 #define ID_DFR0_TRACEFILT_MASK		U(0xf)
 #define ID_DFR0_TRACEFILT_SUPPORTED	U(1)
 
+/* ID_DFR0_EL1 definitions */
+#define ID_DFR0_COPTRC_SHIFT		U(12)
+#define ID_DFR0_COPTRC_MASK		U(0xf)
+#define ID_DFR0_COPTRC_SUPPORTED	U(1)
+
 /* ID_PFR0 definitions */
 #define ID_PFR0_AMU_SHIFT	U(20)
 #define ID_PFR0_AMU_LENGTH	U(4)
@@ -737,4 +742,19 @@
 #define TRFCR		p15, 0, c1, c2, 1
 #define HTRFCR		p15, 4, c1, c2, 1
 
+/*******************************************************************************
+ * Trace System Registers
+ ******************************************************************************/
+#define TRCAUXCTLR	p14, 1, c0, c6,  0
+#define TRCRSR		p14, 1, c0, c10, 0
+#define TRCCCCTLR	p14, 1, c0, c14, 0
+#define TRCBBCTLR	p14, 1, c0, c15, 0
+#define TRCEXTINSELR0	p14, 1, c0, c8,  4
+#define TRCEXTINSELR1	p14, 1, c0, c9,  4
+#define TRCEXTINSELR2	p14, 1, c0, c10, 4
+#define TRCEXTINSELR3	p14, 1, c0, c11, 4
+#define TRCCLAIMSET	p14, 1, c7, c8,  6
+#define TRCCLAIMCLR	p14, 1, c7, c9,  6
+#define TRCDEVARCH	p14, 1, c7, c15, 6
+
 #endif /* ARCH_H */
diff --git a/include/lib/aarch32/arch_features.h b/include/lib/aarch32/arch_features.h
index 7d0ec5f..b61e626 100644
--- a/include/lib/aarch32/arch_features.h
+++ b/include/lib/aarch32/arch_features.h
@@ -42,4 +42,10 @@ static inline bool get_armv8_4_trf_support(void)
 		ID_DFR0_TRACEFILT_SUPPORTED;
 }
 
+static inline bool get_armv8_0_sys_reg_trace_support(void)
+{
+	return ((read_id_dfr0() >> ID_DFR0_COPTRC_SHIFT) &
+		ID_DFR0_COPTRC_MASK) ==
+		ID_DFR0_COPTRC_SUPPORTED;
+}
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index 7bb2d04..6e1097d 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -299,6 +299,19 @@ DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR)
 DEFINE_COPROCR_RW_FUNCS(htrfcr, HTRFCR)
 DEFINE_COPROCR_RW_FUNCS(trfcr, TRFCR)
 
+/* AArch32 Trace System Registers */
+DEFINE_COPROCR_RW_FUNCS(trcauxctlr, TRCAUXCTLR)
+DEFINE_COPROCR_RW_FUNCS(trcrsr, TRCRSR)
+DEFINE_COPROCR_RW_FUNCS(trcbbctlr, TRCBBCTLR)
+DEFINE_COPROCR_RW_FUNCS(trcccctlr, TRCCCCTLR)
+DEFINE_COPROCR_RW_FUNCS(trcextinselr0, TRCEXTINSELR0)
+DEFINE_COPROCR_RW_FUNCS(trcextinselr1, TRCEXTINSELR1)
+DEFINE_COPROCR_RW_FUNCS(trcextinselr2, TRCEXTINSELR2)
+DEFINE_COPROCR_RW_FUNCS(trcextinselr3, TRCEXTINSELR3)
+DEFINE_COPROCR_RW_FUNCS(trcclaimset, TRCCLAIMSET)
+DEFINE_COPROCR_RW_FUNCS(trcclaimclr, TRCCLAIMCLR)
+DEFINE_COPROCR_READ_FUNC(trcdevarch, TRCDEVARCH)
+
 /* AArch32 coproc registers for 32bit MMU descriptor support */
 DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
 DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index f21135d..bcfc333 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -172,6 +172,11 @@
 #define ID_AA64DFR0_TRACEFILT_MASK		U(0xf)
 #define ID_AA64DFR0_TRACEFILT_SUPPORTED		U(1)
 
+/* ID_AA64DFR0_EL1.TraceVer definitions */
+#define ID_AA64DFR0_TRACEVER_SHIFT		U(4)
+#define ID_AA64DFR0_TRACEVER_MASK		ULL(0xf)
+#define ID_AA64DFR0_TRACEVER_SUPPORTED		ULL(1)
+
 #define EL_IMPL_NONE		ULL(0)
 #define EL_IMPL_A64ONLY		ULL(1)
 #define EL_IMPL_A64_A32		ULL(2)
@@ -1025,4 +1030,19 @@
 #define TRFCR_EL1	S3_0_C1_C2_1
 #define TRFCR_EL2	S3_4_C1_C2_1
 
+/*******************************************************************************
+ * Trace System Registers
+ ******************************************************************************/
+#define TRCAUXCTLR	S2_1_C0_C6_0
+#define TRCRSR		S2_1_C0_C10_0
+#define TRCCCCTLR	S2_1_C0_C14_0
+#define TRCBBCTLR	S2_1_C0_C15_0
+#define TRCEXTINSELR0	S2_1_C0_C8_4
+#define TRCEXTINSELR1	S2_1_C0_C9_4
+#define TRCEXTINSELR2	S2_1_C0_C10_4
+#define TRCEXTINSELR3	S2_1_C0_C11_4
+#define TRCCLAIMSET	S2_1_c7_c8_6
+#define TRCCLAIMCLR	S2_1_c7_c9_6
+#define TRCDEVARCH	S2_1_c7_c15_6
+
 #endif /* ARCH_H */
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index fc8ac33..12815ba 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -106,4 +106,11 @@ static inline bool get_armv8_4_trf_support(void)
 		ID_AA64DFR0_TRACEFILT_SUPPORTED;
 }
 
+static inline bool get_armv8_0_sys_reg_trace_support(void)
+{
+        return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEVER_SHIFT) &
+		ID_AA64DFR0_TRACEVER_MASK) ==
+		ID_AA64DFR0_TRACEVER_SUPPORTED;
+}
+
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index b1090d1..2aa42f4 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -502,6 +502,19 @@ DEFINE_RENAME_SYSREG_READ_FUNC(trbidr_el1, TRBIDR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
 
+/* Trace System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcauxctlr, TRCAUXCTLR)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcrsr, TRCRSR)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcbbctlr, TRCBBCTLR)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcccctlr, TRCCCCTLR)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcextinselr0, TRCEXTINSELR0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcextinselr1, TRCEXTINSELR1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcextinselr2, TRCEXTINSELR2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcextinselr3, TRCEXTINSELR3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcclaimset, TRCCLAIMSET)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trcclaimclr, TRCCLAIMCLR)
+DEFINE_RENAME_SYSREG_READ_FUNC(trcdevarch, TRCDEVARCH)
+
 #define IS_IN_EL(x) \
 	(GET_EL(read_CurrentEl()) == MODE_EL##x)
 
diff --git a/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.c b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.c
new file mode 100644
index 0000000..6c28c87
--- /dev/null
+++ b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <tftf.h>
+
+#include "./test_sys_reg_trace.h"
+
+static uint32_t get_trace_arch_ver(void)
+{
+	uint32_t val = read_trcdevarch();
+	val = (val >> TRCDEVARCH_ARCHVER_SHIFT) & TRCDEVARCH_ARCHVER_MASK;
+
+	return val;
+}
+
+/*
+ * EL3 is expected to allow access to trace system registers from EL2.
+ * Reading these register will trap to EL3 and crash when EL3 has not
+ * allowed access.
+ */
+test_result_t test_sys_reg_trace_enabled(void)
+{
+	SKIP_TEST_IF_SYS_REG_TRACE_NOT_SUPPORTED();
+
+	/*
+	 * Read few ETMv4 system trace registers to verify correct access
+	 * been provided from EL3.
+	 */
+	uint32_t trace_arch_ver __unused = get_trace_arch_ver();
+	read_trcauxctlr();
+	read_trcccctlr();
+	read_trcbbctlr();
+	read_trcclaimset();
+	read_trcclaimclr();
+
+	/*
+	 * Read few ETE system trace registers to verify correct access
+	 * been provided from EL3. ETE system trace register access are
+	 * not possible from NS-EL2 in aarch32 state.
+	 */
+#if __aarch64__
+	if (trace_arch_ver == TRCDEVARCH_ARCHVER_ETE) {
+		read_trcrsr();
+		read_trcextinselr0();
+		read_trcextinselr1();
+		read_trcextinselr2();
+		read_trcextinselr3();
+	}
+#endif /* __aarch64__ */
+
+	return TEST_RESULT_SUCCESS;
+}
diff --git a/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.h b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.h
new file mode 100644
index 0000000..640b82c
--- /dev/null
+++ b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TEST_SYS_REG_TRACE_H
+#define TEST_SYS_REG_TRACE_H
+
+/* TRCEDEVARCH definitions */
+#define TRCDEVARCH_ARCHVER_SHIFT	U(12)
+#define TRCDEVARCH_ARCHVER_MASK		U(0xf)
+#define TRCDEVARCH_ARCHVER_ETE		U(0x5)
+
+#endif /* TEST_SYS_REG_TRACE_H */
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index e5f4f79..5ceb340 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -12,6 +12,7 @@ TESTS_SOURCES	+=	$(addprefix tftf/tests/,			\
 	extensions/pauth/test_pauth.c					\
 	extensions/sve/sve_operations.S					\
 	extensions/sve/test_sve.c					\
+	extensions/sys_reg_trace/test_sys_reg_trace.c			\
 	extensions/trbe/test_trbe.c					\
 	extensions/trf/test_trf.c					\
 	runtime_services/arm_arch_svc/smccc_arch_soc_id.c		\
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index a0d2c9a..a1e3f8f 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -22,6 +22,7 @@
     <testcase name="Use ECV Registers" function="test_ecv_enabled" />
     <testcase name="Use trace buffer control Registers" function="test_trbe_enabled" />
     <testcase name="Use trace filter control Registers" function="test_trf_enabled" />
+    <testcase name="Use trace system Registers" function="test_sys_reg_trace_enabled" />
   </testsuite>
 
   <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">