diff options
| author | Manish V Badarkhe <Manish.Badarkhe@arm.com> | 2021-07-08 16:36:57 +0100 |
|---|---|---|
| committer | Manish V Badarkhe <Manish.Badarkhe@arm.com> | 2021-08-26 18:53:50 +0100 |
| commit | 2c518e5c677e7b39100784a0360387b717506564 (patch) | |
| tree | 987cdd4b72d88830568278e5d26953f7f9555e7f /include/lib/aarch32/arch.h | |
| parent | 87c03d1f4c06c1dea78abb359d9b1b4c24470f88 (diff) | |
feat(trf): add trace filter control registers access test
Added a test to read trace filter control registers to ensure that EL3
is giving permission to non-secure EL2 to access these registers.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9354d8592bd187206add717b9d3b0206382a06d3
Diffstat (limited to 'include/lib/aarch32/arch.h')
| -rw-r--r-- | include/lib/aarch32/arch.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 640457b..3ecc047 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -99,6 +99,11 @@ #define ID_MMFR4_CNP_LENGTH U(4) #define ID_MMFR4_CNP_MASK U(0xf) +/* ID_DFR0_EL1 definitions */ +#define ID_DFR0_TRACEFILT_SHIFT U(28) +#define ID_DFR0_TRACEFILT_MASK U(0xf) +#define ID_DFR0_TRACEFILT_SUPPORTED U(1) + /* ID_PFR0 definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) @@ -522,6 +527,7 @@ #define ID_MMFR4 p15, 0, c0, c2, 6 #define ID_PFR0 p15, 0, c0, c1, 0 #define ID_PFR1 p15, 0, c0, c1, 1 +#define ID_DFR0 p15, 0, c0, c1, 2 #define MAIR0 p15, 0, c10, c2, 0 #define MAIR1 p15, 0, c10, c2, 1 #define TTBCR p15, 0, c2, c0, 2 @@ -725,4 +731,10 @@ #define AMEVTYPER1E p15, 0, c13, c15, 6 #define AMEVTYPER1F p15, 0, c13, c15, 7 +/******************************************************************************* + * Armv8.4 - Trace Filter System Registers + ******************************************************************************/ +#define TRFCR p15, 0, c1, c2, 1 +#define HTRFCR p15, 4, c1, c2, 1 + #endif /* ARCH_H */ |