diff options
| author | Petre-Ionut Tudor <petre-ionut.tudor@arm.com> | 2019-10-08 16:51:45 +0100 |
|---|---|---|
| committer | Petre-Ionut Tudor <petre-ionut.tudor@arm.com> | 2019-10-30 15:10:59 +0000 |
| commit | f1a45f767ad6dc31ebde044884f157a1deddbf3c (patch) | |
| tree | 3e9e306ba52936ca52fa73454eaa133335c5ba46 /include/lib/aarch32/arch.h | |
| parent | 2957ff7660eb3b14ed1ee7ade14218332410e3c0 (diff) | |
Aarch32: Secure PMU counter leak tests
This patch adds Aarch32 support to the PMU counter leak tests.
These tests attempt to profile the Secure world by configuring
EL0 system registers such that the PMU is told to increment
counters at Secure EL1, Secure EL2 and EL3. The tests fail if
useful information was leaked.
The Secure world defends against this type of attack with a
combination of configuring EL3 system registers and saving/restoring
EL0 PMU registers. Exactly which defense is employed depends on the
architecture version.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
Diffstat (limited to 'include/lib/aarch32/arch.h')
| -rw-r--r-- | include/lib/aarch32/arch.h | 50 |
1 files changed, 45 insertions, 5 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 3c2a517..dcc4243 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -405,11 +405,45 @@ #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ /* PMCR definitions */ -#define PMCR_N_SHIFT U(11) -#define PMCR_N_MASK U(0x1f) -#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) -#define PMCR_LC_BIT (U(1) << 6) -#define PMCR_DP_BIT (U(1) << 5) +#define PMCR_EL0_N_SHIFT U(11) +#define PMCR_EL0_N_MASK U(0x1f) +#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) +#define PMCR_EL0_LC_BIT (U(1) << 6) +#define PMCR_EL0_DP_BIT (U(1) << 5) +#define PMCR_EL0_E_BIT (U(1) << 0) + +/* PMCNTENSET definitions */ +#define PMCNTENSET_EL0_C_BIT (U(1) << 31) +#define PMCNTENSET_EL0_P_BIT(x) (U(1) << x) + +/* PMEVTYPER<n> definitions */ +#define PMEVTYPER_EL0_P_BIT (U(1) << 31) +#define PMEVTYPER_EL0_NSK_BIT (U(1) << 29) +#define PMEVTYPER_EL0_NSH_BIT (U(1) << 27) +#define PMEVTYPER_EL0_M_BIT (U(1) << 26) +#define PMEVTYPER_EL0_MT_BIT (U(1) << 25) +#define PMEVTYPER_EL0_SH_BIT (U(1) << 24) +#define PMEVTYPER_EL0_EVTCOUNT_BITS U(0x000003FF) + +/* PMCCFILTR definitions */ +#define PMCCFILTR_EL0_P_BIT (U(1) << 31) +#define PMCCFILTR_EL0_NSK_BIT (U(1) << 29) +#define PMCCFILTR_EL0_NSH_BIT (U(1) << 27) +#define PMCCFILTR_EL0_M_BIT (U(1) << 26) +#define PMCCFILTR_EL0_MT_BIT (U(1) << 25) +#define PMCCFILTR_EL0_SH_BIT (U(1) << 24) + +/* PMU event counter ID definitions */ +#define PMU_EV_PC_WRITE_RETIRED U(0x000C) + +/* DBGDIDR definitions */ +#define DBGDIDR_VERSION_SHIFT U(16) +#define DBGDIDR_VERSION_MASK U(0xf) +#define DBGDIDR_VERSION_BITS (DBGDIDR_VERSION_MASK << DBGDIDR_VERSION_SHIFT) +#define DBGDIDR_V8_DEBUG_ARCH_SUPPORTED U(6) +#define DBGDIDR_V8_DEBUG_ARCH_VHE_SUPPORTED U(7) +#define DBGDIDR_V8_2_DEBUG_ARCH_SUPPORTED U(8) +#define DBGDIDR_V8_4_DEBUG_ARCH_SUPPORTED U(9) /******************************************************************************* * Definitions of register offsets, fields and macros for CPU system @@ -522,6 +556,12 @@ /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ #define HDCR p15, 4, c1, c1, 1 #define PMCR p15, 0, c9, c12, 0 +#define PMCNTENSET p15, 0, c9, c12, 1 +#define PMCCFILTR p15, 0, c14, c15, 7 +#define PMCCNTR p15, 0, c9, c13, 0 +#define PMEVTYPER0 p15, 0, c14, c12, 0 +#define PMEVCNTR0 p15, 0, c14, c8, 0 +#define DBGDIDR p14, 0, c0, c0, 0 #define CNTHP_TVAL p15, 4, c14, c2, 0 #define CNTHP_CTL p15, 4, c14, c2, 1 |