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Add tests to confirm that the em_version, em_features and
em_cpu_erratum_features calls conform to the errata abi spec.
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: I8395026acc004a10d8c2c17ec689f4e0752143d8
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This patch adds Realm PMU payload tests with
PMU interrupt handling.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2
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This patch adds Realm payload management capabilities to TFTF
to act as a NS Host, it includes creation and destruction of a Realm,
mapping of protected data and creation of all needed RTT levels,
sharing of NS memory buffer from Host to Realm by mapping of
unprotected IPA, create REC and auxiliary granules, exit Realm
using RSI_HOST_CALL ABI.
Older realm_payload name is used now for only R-EL1 test cases,
RMI and SPM test cases have been moved to new file tests-rmi-spm.
New TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,
as an offset from where R-EL1 payload memory resources start.
Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com>
Change-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7
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Added a test to read trace system registers to ensure that EL3
is giving permission to non-secure EL2 to access these registers.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I0bdbb5aff81a78fc3a3766278c48b25bb6e1779f
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Added a test to read trace filter control registers to ensure that EL3
is giving permission to non-secure EL2 to access these registers.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9354d8592bd187206add717b9d3b0206382a06d3
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Not much can be done with the new AMU offsets running at EL2 (virtual
offsets apply at EL0 and EL1) but we can make sure they are being saved
and restored properly, so that's what this patch does.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5aef85021e875be2109bb9bd7cdbdbe31580394e
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This patch adds Aarch32 support to the PMU counter leak tests.
These tests attempt to profile the Secure world by configuring
EL0 system registers such that the PMU is told to increment
counters at Secure EL1, Secure EL2 and EL3. The tests fail if
useful information was leaked.
The Secure world defends against this type of attack with a
combination of configuring EL3 system registers and saving/restoring
EL0 PMU registers. Exactly which defense is employed depends on the
architecture version.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
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Change-Id: I0509065512907217dc17c0ec5ce474e2bb8d4e89
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Change-Id: Ieb56d0639efd29c2695751b2b36cc98ce2c90dab
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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At the moment, no information is printed on the UART whenever we hit
an unexpected exception, not even an error message. This is not great
from the user's perspective, who has got no idea of what is going on.
Now we print an error message, as well as the state of some of the
registers. This includes general-purpose registers, as well as some
system registers.
This is implemented for TFTF running:
- in AArch64 state, at EL2;
- in AArch64 state, at NS-EL1;
- in AArch32 state.
We might want to dump more registers in the future but this patch
at least provides a basis we can build upon.
Also, the SP_EL0 has been removed from the list of registers saved in
the CPU context because TFTF always uses SP_ELx and does not touch
SP_EL0 at all.
Change-Id: I56e4afa917b53b5ccccff1d5d09ac8ccfaa6ae49
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Change-Id: Ia4850f58f4519a71a049290839027ea7a0521415
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Hardcoding CPU to affinity level 0 and cluster to level 1 isn't correct.
This patch removes the definitions from arch.h to prevent more tests from
making this assumption. It doesn't fix the tests that are already using
them as it may be needed to do more changes to make the tests truly
generic.
Change-Id: I3e5362ef7db7769f7db98ba68ad3842f5baa3e60
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Some of the affected macros can only be used from C code. In general, we
use arch_helpers.h for any C helpers to access registers. For
consistency, the other macros have been moved as well.
Change-Id: If27ee82b067d920d7b338c0a1b6e61a6ec078f4f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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The headers forked at some point in the past and have diverged a lot. In
order to make it easier to share code between TF-A-Tests and TF-A, this
patch synchronises most of the definitions in the mentioned headers.
This is not a complete sync, it has to be followed by more cleanup.
Change-Id: I35c1b928cb4c06ae52483406c933e5f11cb47bf8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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This is the first public version of the tests for the Trusted
Firmware-A project. Please see the documentation provided in the
source tree for more details.
Change-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: amobal01 <amol.balasokamble@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Co-authored-by: Asha R <asha.r@arm.com>
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Co-authored-by: David Cunado <david.cunado@arm.com>
Co-authored-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Co-authored-by: Douglas Raillard <douglas.raillard@arm.com>
Co-authored-by: dp-arm <dimitris.papastamos@arm.com>
Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Co-authored-by: Jonathan Wright <jonathan.wright@arm.com>
Co-authored-by: Kévin Petit <kevin.petit@arm.com>
Co-authored-by: Roberto Vargas <roberto.vargas@arm.com>
Co-authored-by: Sathees Balya <sathees.balya@arm.com>
Co-authored-by: Shawon Roy <Shawon.Roy@arm.com>
Co-authored-by: Soby Mathew <soby.mathew@arm.com>
Co-authored-by: Thomas Abraham <thomas.abraham@arm.com>
Co-authored-by: Vikram Kanigiri <vikram.kanigiri@arm.com>
Co-authored-by: Yatharth Kochar <yatharth.kochar@arm.com>
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