path: root/arch/arm64/boot/dts/mediatek/mt8173.dtsi

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Eddie Huang <eddie.huang@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/mt8173-resets.h>
#include "mt8173-pinfunc.h"
#include <dt-bindings/clock/mt8173-clk.h>

/ {
	compatible = "mediatek,mt8173";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			clocks = <&infracfg INFRA_CA53SEL>, <&apmixedsys APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points = <
				1508000 1109000
				1404000	1083000
				1183000	1028000
				1105000	1009000
				1001000	 983000
				 702000	 908000
				 507000	 859000
			>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x100>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			clocks = <&infracfg INFRA_CA57SEL>, <&apmixedsys APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points = <
				1807000	1089000
				1612000	1049000
				1404000	1007000
				1209000	 968000
				1001000	 927000
				 702000	 867000
				 507000	 828000
			>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x101>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <639>;
				exit-latency-us = <328>;
				min-residency-us = <1088>;
			};
 		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend   = <0x84000001>;
		cpu_off	      = <0x84000002>;
		cpu_on	      = <0x84000003>;
	};

	clocks {
		clk_null: clk_null {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		clk26m: clk26m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};

		clk32k: clk32k {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		syscfg_pctl_a: syscfg_pctl_a@10005000 {
			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
			reg = <0 0x10005000 0 0x1000>;
		};

		pio: pinctrl@0x10005000 {
			compatible = "mediatek,mt8173-pinctrl";
			reg = <0 0x1000B000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl_a>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

			i2c0_pins_a: i2c0@0 {
				pins1 {
					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
						<MT8173_PIN_46_SCL0__FUNC_SCL0>;
					bias-disable;
				};
			};

			i2c1_pins_a: i2c1@0 {
				pins1 {
					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
						<MT8173_PIN_126_SCL1__FUNC_SCL1>;
					bias-disable;
				};
			};

			i2c2_pins_a: i2c2@0 {
				pins1 {
					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
						<MT8173_PIN_44_SCL2__FUNC_SCL2>;
					bias-disable;
				};
			};

			i2c3_pins_a: i2c3@0 {
				pins1 {
					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
						<MT8173_PIN_107_SCL3__FUNC_SCL3>;
					bias-disable;
				};
			};

			i2c4_pins_a: i2c4@0 {
				pins1 {
					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
						<MT8173_PIN_134_SCL4__FUNC_SCL4>;
					bias-disable;
				};
			};

			i2c6_pins_a: i2c6@0 {
				pins1 {
					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
						<MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
					bias-disable;
				};
			};
		};

		topckgen: topckgen@10000000 {
			compatible = "mediatek,mt8173-topckgen";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		i2c0: i2c@11007000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11007000 0 0x70>,
				<0 0x11000100 0 0x80>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg PERI_I2C2>, <&pericfg PERI_AP_DMA>;
			clock-names = "main", "dma";
		};

		i2c1: i2c@11008000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11008000 0 0x70>,
				<0 0x11000180 0 0x80>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg PERI_I2C2>, <&pericfg PERI_AP_DMA>;
			clock-names = "main", "dma";
		};

		i2c2: i2c@11009000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11009000 0 0x70>,
				<0 0x11000200 0 0x80>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg PERI_I2C2>, <&pericfg PERI_AP_DMA>;
			clock-names = "main", "dma";
		};

		i2c3: i2c3@0x11010000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11010000 0 0x70>,
				<0 0x11000280 0 0x80>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg PERI_I2C3>, <&pericfg PERI_AP_DMA>;
			clock-names = "main", "dma";
		};

		i2c4: i2c4@0x11011000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11011000 0 0x70>,
				<0 0x11000300 0 0x80>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg PERI_I2C4>, <&pericfg PERI_AP_DMA>;
			clock-names = "main", "dma";
		};

		i2c6: i2c6@0x11013000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11013000 0 0x70>,
				<0 0x11000080 0 0x80>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg PERI_I2C6>, <&pericfg PERI_AP_DMA>;
			clock-names = "main", "dma";
		};

		infracfg: infracfg@10001000 {
			compatible = "mediatek,mt8173-infracfg";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: pericfg@10003000 {
			compatible = "mediatek,mt8173-pericfg";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		sysirq: intpol-controller@10200620 {
			compatible = "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200620 0 0x20>;
		};

		pwrap: pwrap@1000D000 {
			compatible = "mediatek,mt8173-pwrap";
			reg = <0 0x1000D000 0 0x1000>;
			reg-names = "pwrap-base";
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
			reset-names = "pwrap";
			clocks = <&infracfg INFRA_PMICSPI>, <&infracfg INFRA_PMICWRAP>;
			clock-names = "spi", "wrap";
		};

		apmixedsys: apmixedsys@10209000 {
			compatible = "mediatek,mt8173-apmixedsys";
			reg = <0 0x10209000 0 0x1000>;
			#clock-cells = <1>;
		};

		gic: interrupt-controller@10220000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x10221000 0 0x1000>,
			      <0 0x10222000 0 0x2000>,
			      <0 0x10224000 0 0x2000>,
			      <0 0x10226000 0 0x2000>;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt8173-mmc","mediatek,mt8135-mmc";
			reg = <0 0x11230000 0 0x108>;
			interrupts = <0 71 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg PERI_MSDC30_0>;
			clock-names = "source";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt8173-mmc","mediatek,mt8135-mmc";
			reg = <0 0x11240000 0 0x108>;
			interrupts = <0 72 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg PERI_MSDC30_1>;
			clock-names = "source";
			status = "disabled";
		};

		scpsys: scpsys@10001000 {
			compatible = "mediatek,mt8173-scpsys";
			reg = <0 0x10001000 0 0x1000>, <0 0x10006000 0 0x1000>, <0 0x13fff000 0 0x1000>;
			#clock-cells = <1>;
		};

		u3phy: usb-phy@11271000 {
			compatible = "mediatek,mt8173-u3phy";
			reg = <0 0x11271000 0 0x3000>,
				<0 0x11280000 0 0x20000>;
			usb-host = <&usb>;
			reg-vusb33-supply = <&mt6397_vusb_reg>;
			usb3_ref_clk = <&apmixedsys>;
			clocks = <&scpsys 10>,
				<&pericfg PERI_USB0>,
				<&pericfg PERI_USB1>;
			clock-names = "scp_sys_usb", "peri_usb0", "peri_usb1";
		};

		usb: usb30@11270000 {
			compatible = "mediatek,mt8173-xhci", "generic-xhci";
			reg = <0 0x11270000 0 0x1000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
			mediatek,phy = <&u3phy>;
		};
	};

};