arm64: qcom: msm8996: db820c: Add CPR3 HMSS description

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

2 files changed, 249 insertions, 8 deletions

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 2d81291cadf3..790b500320c9 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -663,11 +663,11 @@
 	s10 {
 		qcom,saw-slave;
 	};
-	s11 {
+	pmi8994_s11: s11 {
 		qcom,saw-leader;
 		regulator-always-on;
-		regulator-min-microvolt = <980000>;
-		regulator-max-microvolt = <980000>;
+		regulator-min-microvolt = <470000>;
+		regulator-max-microvolt = <1140000>;
 	};
 };
 
@@ -988,6 +988,10 @@
 	};
 };
 
+&apcc_cpr3 {
+	vdd-supply = <&pmi8994_s11>;
+};
+
 &sdhc2 {
 	/* External SD card */
 	pinctrl-names = "default", "sleep";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 52df22ab3f6a..064bc9c25c9a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -47,6 +47,8 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&kryocc 0>;
 			operating-points-v2 = <&cluster0_opp>;
+			power-domains = <&apcc_cpr3>;
+			power-domain-names = "hmss_cpr3";
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
@@ -64,6 +66,8 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&kryocc 0>;
 			operating-points-v2 = <&cluster0_opp>;
+			power-domains = <&apcc_cpr3>;
+			power-domain-names = "hmss_cpr3";
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_0>;
 		};
@@ -77,6 +81,10 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&kryocc 1>;
 			operating-points-v2 = <&cluster1_opp>;
+			/*
+			power-domains = <&apcc_cpr3>;
+			power-domain-names = "hmss_cpr3";
+			*/
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
@@ -94,6 +102,10 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&kryocc 1>;
 			operating-points-v2 = <&cluster1_opp>;
+			/*
+			power-domains = <&apcc_cpr3>;
+			power-domain-names = "hmss_cpr3";
+			*/
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_1>;
 		};
@@ -649,6 +661,156 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			speedbin_efuse: speedbin@133 {
+				reg = <0x133 0x1>;
+				bits = <5 3>;
+			};
+
+			cpr_revision: revision@13e {
+				reg = <0x13e 0x1>;
+				bits = <3 3>;
+			};
+
+			cpr1_ring_turbo: cpr1_ring_turbo@205 {
+				reg = <0x205 0x2>;
+				bits = <6 4>;
+			};
+
+			cpr1_ring_nom: cpr1_ring_nom@206 {
+				reg = <0x206 0x1>;
+				bits = <2 4>;
+			};
+
+			cpr1_ring_svs: cpr1_ring_svs@206 {
+				reg = <0x206 0x2>;
+				bits = <6 4>;
+			};
+
+			cpr1_init_voltage_turbo: cpr1_init_voltage_turbo@207 {
+				reg = <0x207 0x2>;
+				bits = <6 6>;
+			};
+
+			cpr1_init_voltage_nom: cpr1_init_voltage_nom@208 {
+				reg = <0x208 0x2>;
+				bits = <4 6>;
+			};
+
+			cpr1_init_voltage_svs: cpr1_init_voltage_svs@209 {
+				reg = <0x209 0x1>;
+				bits = <2 6>;
+			};
+
+			cpr1_init_voltage_minsvs: cpr1_init_voltage_minsvs@20a {
+				reg = <0x20a 0x1>;
+				bits = <0 6>;
+			};
+
+			cpr1_quot_turbo: cpr1_quot_turbo@20a {
+				reg = <0x20a 0x3>;
+				bits = <6 12>;
+			};
+
+			cpr1_quot_nom: cpr1_quot_nom@20c {
+				reg = <0x20c 0x2>;
+				bits = <2 12>;
+			};
+
+			cpr1_quot_svs: cpr1_quot_svs@20d {
+				reg = <0x20d 0x3>;
+				bits = <6 12>;
+			};
+
+			cpr1_quot_minsvs: cpr1_quot_minsvs@20f {
+				reg = <0x20f 0x2>;
+				bits = <2 12>;
+			};
+
+			cpr1_quot_offset_turbo: cpr1_quot_offset_turbo@210 {
+				reg = <0x210 0x2>;
+				bits = <6 8>;
+			};
+
+			cpr1_quot_offset_nom: cpr1_quot_offset_nom@211 {
+				reg = <0x211 0x2>;
+				bits = <6 8>;
+			};
+
+			cpr1_quot_offset_svs: cpr1_quot_offset_svs@212 {
+				reg = <0x212 0x2>;
+				bits = <6 8>;
+			};
+
+			cpr0_ring_turbo: cpr0_ring_turbo@213 {
+				reg = <0x213 0x2>;
+				bits = <6 4>;
+			};
+
+			cpr0_ring_nom: cpr0_ring_nom@214 {
+				reg = <0x214 0x1>;
+				bits = <2 4>;
+			};
+
+			cpr0_ring_svs: cpr0_ring_svs@214 {
+				reg = <0x214 0x2>;
+				bits = <6 4>;
+			};
+
+			cpr0_init_voltage_turbo: cpr0_init_voltage_turbo@215 {
+				reg = <0x215 0x2>;
+				bits = <6 6>;
+			};
+
+			cpr0_init_voltage_nom: cpr0_init_voltage_nom@216 {
+				reg = <0x216 0x2>;
+				bits = <4 6>;
+			};
+
+			cpr0_init_voltage_svs: cpr0_init_voltage_svs@217 {
+				reg = <0x217 0x1>;
+				bits = <2 6>;
+			};
+
+			cpr0_init_voltage_minsvs: cpr0_init_voltage_minsvs@218 {
+				reg = <0x218 0x1>;
+				bits = <0 6>;
+			};
+
+			cpr0_quot_turbo: cpr0_quot_turbo@218 {
+				reg = <0x218 0x3>;
+				bits = <6 12>;
+			};
+
+			cpr0_quot_nom: cpr0_quot_nom@21a {
+				reg = <0x21a 0x2>;
+				bits = <2 12>;
+			};
+
+			cpr0_quot_svs: cpr0_quot_svs@21b {
+				reg = <0x21b 0x3>;
+				bits = <6 12>;
+			};
+
+			cpr0_quot_minsvs: cpr0_quot_minsvs@21d {
+				reg = <0x21d 0x2>;
+				bits = <2 12>;
+			};
+
+			cpr0_quot_offset_turbo: cpr0_quot_offset_turbo@21e {
+				reg = <0x21e 0x2>;
+				bits = <6 8>;
+			};
+
+			cpr0_quot_offset_nom: cpr0_quot_offset_nom@21f {
+				reg = <0x21f 0x2>;
+				bits = <6 8>;
+			};
+
+			cpr0_quot_offset_svs: cpr0_quot_offset_svs@220 {
+				reg = <0x220 0x2>;
+				bits = <6 8>;
+			};
+
 			qusb2p_hstx_trim: hstx_trim@24e {
 				reg = <0x24e 0x2>;
 				bits = <5 4>;
@@ -658,11 +820,6 @@
 				reg = <0x24f 0x1>;
 				bits = <1 4>;
 			};
-
-			speedbin_efuse: speedbin@133 {
-				reg = <0x133 0x1>;
-				bits = <5 3>;
-			};
 		};
 
 		rng: rng@83000 {
@@ -3096,6 +3253,86 @@
 			};
 		};
 
+		apcc_cpr3: power-controller@99e8000 {
+			compatible = "qcom,msm8996-cpr3-hmss";
+			reg = <0x099e8000 0x4000>;
+			clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
+			clock-names = "ref";
+			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "cpr", "ceiling";
+			#power-domain-cells = <0>;
+			operating-points-v2 = <&apcc_cpr3_0_opp_table>;
+			acc-syscon = <&tcsr>;
+
+			nvmem-cells =
+				<&cpr1_quot_offset_svs>,
+				<&cpr1_quot_offset_nom>,
+				<&cpr1_quot_offset_turbo>,
+				<&cpr1_init_voltage_minsvs>,
+				<&cpr1_init_voltage_svs>,
+				<&cpr1_init_voltage_svs>,
+				<&cpr1_init_voltage_nom>,
+				<&cpr1_init_voltage_turbo>,
+				<&cpr1_quot_minsvs>,
+				<&cpr1_quot_svs>,
+				<&cpr1_quot_svs>,
+				<&cpr1_quot_nom>,
+				<&cpr1_quot_turbo>,
+				<&cpr1_ring_svs>,
+				<&cpr1_ring_svs>,
+				<&cpr1_ring_svs>,
+				<&cpr1_ring_nom>,
+				<&cpr1_ring_turbo>,
+				<&cpr_revision>,
+				<&speedbin_efuse>;
+			nvmem-cell-names =
+				"cpr0_quotient_offset3",
+				"cpr0_quotient_offset4",
+				"cpr0_quotient_offset5",
+				"cpr0_init_voltage1",
+				"cpr0_init_voltage2",
+				"cpr0_init_voltage3",
+				"cpr0_init_voltage4",
+				"cpr0_init_voltage5",
+				"cpr0_quotient1",
+				"cpr0_quotient2",
+				"cpr0_quotient3",
+				"cpr0_quotient4",
+				"cpr0_quotient5",
+				"cpr0_ring_osc1",
+				"cpr0_ring_osc2",
+				"cpr0_ring_osc3",
+				"cpr0_ring_osc4",
+				"cpr0_ring_osc5",
+				"cpr_fuse_revision",
+				"cpr_speed_bin";
+
+			apcc_cpr3_0_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp1 {
+					opp-level = <0>; /* minsvs */
+				};
+
+				opp2 {
+					opp-level = <1>; /* lowsvs */
+				};
+
+				opp3 {
+					opp-level = <2>; /* svs */
+				};
+
+				opp4 {
+					opp-level = <3>; /* nom */
+				};
+
+				opp5 {
+					opp-level = <4>; /* turbo */
+				};
+			};
+		};
+
 		saw3: syscon@9a10000 {
 			compatible = "syscon";
 			reg = <0x09a10000 0x1000>;