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-rw-r--r--notify/mail-body.txt38
1 files changed, 22 insertions, 16 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index 3b207d8..e3a0242 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -2,22 +2,28 @@ Dear contributor, our automatic CI has detected problems related to your patch(e
In CI config tcwg_bmk-code_size-coremark/gnu_eabi-arm_eabi-master-Os_LTO after:
- | 85 commits in binutils,gcc
- | 1d8f691da90 Automatic date update in version.in
- | 23b5268986d Automatic date update in version.in
- | 4ebfd53de03 Support the NO_COLOR environment variable
- | 2677a57064a tc-microblaze.c - int compare for X_add_number.
- | 54fd15eef72 bfd: microblaze: Fix bug in TLSTPREL Relocation
- | ... and 30 more commits in binutils
- | 125781fb2c9 Daily bump.
- | 04e772bbdcb RISC-V: Use safe_grow_cleared for vector info [PR111649]
- | 1e6815071fd gimple-match-head: Fix a pasto in function comment
- | 09b512466ce lowerbitint: Fix 2 bitint lowering bugs [PR111625]
- | 9d249b7e31e vec.h: Uncomment static_assert
- | ... and 45 more commits in gcc
+ | 392 commits in binutils,gcc,newlib
+ | 9326300e4d3 RISC-V: Add support for numbered ISA mapping strings
+ | 5772d798236 Move -lsocket check to common.m4
+ | 59fed66dcef Automatic date update in version.in
+ | 07c833f99c3 Fix test suite failure in file-then-restart.exp
+ | b8ead7d503a bfd: add new bfd_cache_size() function
+ | ... and 127 more commits in binutils
+ | 0f40e59f193 RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
+ | f0b05073bd3 RISC-V: Leverage stdint-gcc.h for RVV test cases
+ | 8f52040e5f0 RISC-V: Support FP lfloor/lfloorf auto vectorization
+ | ba0cde8ba2d testsuite: Replace many dg-require-thread-fence with dg-require-atomic-cmpxchg-word
+ | 2a4d9e4f533 testsuite: Add dg-require-atomic-cmpxchg-word
+ | ... and 250 more commits in gcc
+ | fbc5496e4 sparc: Improve setjmp()
+ | 696c282cf riscv: Fix fenv.h support
+ | dcb2b7d7b Delete check in catan, catanf, and catanl functions.
+ | fe5886a50 aarch64: Import memrchr.S
+ | 96ec8f868 aarch64: Sync with ARM-software/optimized-routines
No change
+The configuration of this build is:
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI.
Configuration:
@@ -25,7 +31,7 @@ Configuration:
- Toolchain: GCC + Newlib + GNU LD
- Version: all components were built from their tip of trunk
- Target: arm-eabi
-- Compiler flags: Os -flto
+- Compiler flags: Os -LTO
- Hardware: STMicroelectronics STM32L476RGTx 1x Cortex-M4
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain@lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
@@ -33,6 +39,6 @@ This benchmarking CI is work-in-progress, and we welcome feedback and suggestion
-----------------8<--------------------------8<--------------------------8<--------------------------
The information below can be used to reproduce a debug environment:
-Current build : https://ci.linaro.org/job/tcwg_bmk-code_size-coremark--gnu_eabi-arm_eabi-master-Os_LTO-build/89/artifact/artifacts
-Reference build : https://ci.linaro.org/job/tcwg_bmk-code_size-coremark--gnu_eabi-arm_eabi-master-Os_LTO-build/88/artifact/artifacts
+Current build : https://ci.linaro.org/job/tcwg_bmk-code_size-coremark--gnu_eabi-arm_eabi-master-Os_LTO-build/93/artifact/artifacts
+Reference build : https://ci.linaro.org/job/tcwg_bmk-code_size-coremark--gnu_eabi-arm_eabi-master-Os_LTO-build/89/artifact/artifacts