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-rw-r--r--notify/jira/comment-card.txt3
-rw-r--r--notify/jira/comment-template.txt5
-rw-r--r--notify/jira/components1
-rw-r--r--notify/jira/description48
-rw-r--r--notify/jira/key1
-rw-r--r--notify/jira/startdate1
-rw-r--r--notify/jira/summary1
-rw-r--r--notify/jira/yaml56
8 files changed, 114 insertions, 2 deletions
diff --git a/notify/jira/comment-card.txt b/notify/jira/comment-card.txt
new file mode 100644
index 0000000..afdf437
--- /dev/null
+++ b/notify/jira/comment-card.txt
@@ -0,0 +1,3 @@
+[LLVM-928]
+453.povray:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+Details: https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-aarch64-master-O3-build/60/artifact/artifacts/notify/mail-body.txt/*view*/
diff --git a/notify/jira/comment-template.txt b/notify/jira/comment-template.txt
index 2a2f47b..6a7baad 100644
--- a/notify/jira/comment-template.txt
+++ b/notify/jira/comment-template.txt
@@ -1,3 +1,4 @@
[LLVM-651]
-No change
-Details: https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-aarch64-master-O3-build/59/artifact/artifacts/notify/mail-body.txt/*view*/
+https://linaro.atlassian.net/browse/LLVM-928
+453.povray:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+Details: https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-aarch64-master-O3-build/60/artifact/artifacts/notify/mail-body.txt/*view*/
diff --git a/notify/jira/components b/notify/jira/components
new file mode 100644
index 0000000..8072713
--- /dev/null
+++ b/notify/jira/components
@@ -0,0 +1 @@
+LLVM
diff --git a/notify/jira/description b/notify/jira/description
new file mode 100644
index 0000000..680a272
--- /dev/null
+++ b/notify/jira/description
@@ -0,0 +1,48 @@
+commit llvmorg-18-init-5853-gcbdccb30c23f
+Author: Guozhi Wei <carrot@google.com>
+Date: Fri Sep 15 19:52:50 2023 +0000
+
+ [RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
+
+ If a virtual register is not assigned preferred physical register, it means some
+ COPY instructions will be changed to real register move instructions. In this
+ case we can try to split the virtual register in colder blocks, if success, the
+ original COPY instructions can be deleted, and the new COPY instructions in
+ colder blocks will be generated as register move instructions. It results in
+... 7 lines of the commit log omitted.
+
+* tcwg_bmk-code_size-cpu2017fast
+** llvm-aarch64-master-O3
+*** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017fast/llvm-aarch64-master-O3/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017fast--llvm-aarch64-master-O3-build/71/
+* tcwg_bmk-code_size-cpu2017rate
+** llvm-arm-master-O2
+*** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017rate/llvm-arm-master-O2/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017rate--llvm-arm-master-O2-build/70/
+** llvm-arm-master-O3
+*** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 11%
+*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017rate/llvm-arm-master-O3/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017rate--llvm-arm-master-O3-build/59/
+* tcwg_bmk-code_size-spec2k6
+** llvm-aarch64-master-O3
+*** 453.povray:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+*** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-spec2k6/llvm-aarch64-master-O3/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-aarch64-master-O3-build/60/
+** llvm-arm-master-Os
+*** 401.bzip2 grew in size by 9%
+*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-spec2k6/llvm-arm-master-Os/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-arm-master-Os-build/71/
+* tcwg_bmk-code_speed-cpu2017rate
+** llvm-aarch64-master-O3
+*** 526.blender_r slowed down by 4%
+*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_speed-cpu2017rate/llvm-aarch64-master-O3/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-aarch64-master-O3-build/98/
+* tcwg_bmk-fujitsu_speed-cpu2017speed
+** llvm-aarch64-master-O3
+*** 641.leela_s:[.] _ZN9FastState16play_random_moveEi slowed down by 32%
+*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-fujitsu_speed-cpu2017speed/llvm-aarch64-master-O3/details.txt
+*** https://ci.linaro.org/job/tcwg_bmk-fujitsu_speed-cpu2017speed--llvm-aarch64-master-O3-build/149/
+
+Latest data: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/jira/yaml
diff --git a/notify/jira/key b/notify/jira/key
new file mode 100644
index 0000000..646e87e
--- /dev/null
+++ b/notify/jira/key
@@ -0,0 +1 @@
+LLVM-928
diff --git a/notify/jira/startdate b/notify/jira/startdate
new file mode 100644
index 0000000..4ef0b1a
--- /dev/null
+++ b/notify/jira/startdate
@@ -0,0 +1 @@
+2023-09-15
diff --git a/notify/jira/summary b/notify/jira/summary
new file mode 100644
index 0000000..4b40b59
--- /dev/null
+++ b/notify/jira/summary
@@ -0,0 +1 @@
+llvmorg-18-init-5853-gcbdccb30c23f: 453.povray:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
diff --git a/notify/jira/yaml b/notify/jira/yaml
new file mode 100644
index 0000000..e2a7034
--- /dev/null
+++ b/notify/jira/yaml
@@ -0,0 +1,56 @@
+- Project: LLVM
+ IssueType: Sub-task
+ Key: LLVM-928
+ Summary: |
+ llvmorg-18-init-5853-gcbdccb30c23f: 453.povray:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+ Components: LLVM
+ Start date: 2023-09-15
+ Description: |
+ commit llvmorg-18-init-5853-gcbdccb30c23f
+ Author: Guozhi Wei <carrot@google.com>
+ Date: Fri Sep 15 19:52:50 2023 +0000
+
+ [RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
+
+ If a virtual register is not assigned preferred physical register, it means some
+ COPY instructions will be changed to real register move instructions. In this
+ case we can try to split the virtual register in colder blocks, if success, the
+ original COPY instructions can be deleted, and the new COPY instructions in
+ colder blocks will be generated as register move instructions. It results in
+ ... 7 lines of the commit log omitted.
+
+ * tcwg_bmk-code_size-cpu2017fast
+ ** llvm-aarch64-master-O3
+ *** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+ *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017fast/llvm-aarch64-master-O3/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017fast--llvm-aarch64-master-O3-build/71/
+ * tcwg_bmk-code_size-cpu2017rate
+ ** llvm-arm-master-O2
+ *** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+ *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017rate/llvm-arm-master-O2/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017rate--llvm-arm-master-O2-build/70/
+ ** llvm-arm-master-O3
+ *** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 11%
+ *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017rate/llvm-arm-master-O3/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017rate--llvm-arm-master-O3-build/59/
+ * tcwg_bmk-code_size-spec2k6
+ ** llvm-aarch64-master-O3
+ *** 453.povray:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
+ *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-spec2k6/llvm-aarch64-master-O3/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-aarch64-master-O3-build/60/
+ ** llvm-arm-master-Os
+ *** 401.bzip2 grew in size by 9%
+ *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-spec2k6/llvm-arm-master-Os/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-code_size-spec2k6--llvm-arm-master-Os-build/71/
+ * tcwg_bmk-code_speed-cpu2017rate
+ ** llvm-aarch64-master-O3
+ *** 526.blender_r slowed down by 4%
+ *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_speed-cpu2017rate/llvm-aarch64-master-O3/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-aarch64-master-O3-build/98/
+ * tcwg_bmk-fujitsu_speed-cpu2017speed
+ ** llvm-aarch64-master-O3
+ *** 641.leela_s:[.] _ZN9FastState16play_random_moveEi slowed down by 32%
+ *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-fujitsu_speed-cpu2017speed/llvm-aarch64-master-O3/details.txt
+ *** https://ci.linaro.org/job/tcwg_bmk-fujitsu_speed-cpu2017speed--llvm-aarch64-master-O3-build/149/
+
+ Latest data: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/jira/yaml
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 16:03:29 +0000