diff options
Diffstat (limited to 'notify/mail-body.txt')
| -rw-r--r-- | notify/mail-body.txt | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt index aad9a92..20f3071 100644 --- a/notify/mail-body.txt +++ b/notify/mail-body.txt @@ -2,19 +2,25 @@ Dear contributor, our automatic CI has detected problems related to your patch(e In CI config tcwg_kernel/llvm-master-aarch64-lts-allnoconfig after: - | 329 commits in binutils,llvm - | 11788869e0a Automatic date update in version.in - | 1e62d51f295 Automatic date update in version.in - | 8fbb497b720 gas: bpf: do not allow referring to register names as symbols in operands - | 26c7a0ea380 Automatic date update in version.in - | e5d6f72eb3d bpf: avoid creating wrong symbols while parsing - | ... and 36 more commits in binutils - | a2e1de193477 [ARM][FPEnv] Lowering of fpenv intrinsics - | 592386400d51 [PowerPC] Precommit test to show codegen while `isel` is unavailable. NFC. - | d572c4cdef4b [PowerPC] Disable float128 on AIX in Clang (#67298) - | c1fe1900491a Revert "Add new API in SBTarget for loading core from SBFile (#71769)" - | 7cc54da16f25 Add @MaheshRavishankar to CODEOWNERS on relevant source files. (#72449) - | ... and 283 more commits in llvm + | 595 commits in binutils,llvm,qemu + | 2ec31e54dff RISC-V: drop leftover match_never() references + | d3b01414b93 x86: shrink opcode sets table + | 39bb3ade816 x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible + | eb5e952f954 RISC-V: reduce redundancy in sign/zero extension macro insn handling + | 27b33966b18 RISC-V: disallow x0 with certain macro-insns + | ... and 70 more commits in binutils + | 25b5e5c4e9a3 Update links in AttrDocs.td for coro_lifetimebound + | b98a594977f2 [clang][analyzer] Move `security.cert.env.InvalidPtr` out of `alpha` (#71912) + | dd0b3c2fa627 [clang][analyzer] Support `fprintf` in the SecuritySyntaxChecker (#73247) + | 579e721ce91b [Support] Implement getMainExecutable for Haiku + | d80e46da7d20 [RISCV] Support target attribute for function + | ... and 411 more commits in llvm + | b93c4313f2 Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging + | 2ebe6659ec Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa into staging + | 6bca4d7d1f target/riscv/cpu_helper.c: Fix mxr bit behavior + | 82d53adfbb target/riscv/cpu_helper.c: Invalid exception on MMU translation stage + | a7472560ca riscv: Fix SiFive E CLINT clock frequency + | ... and 99 more commits in qemu Results changed to # reset_artifacts: @@ -54,6 +60,6 @@ CI config tcwg_kernel/llvm-master-aarch64-lts-allnoconfig -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: -Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allnoconfig-build/72/artifact/artifacts -Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allnoconfig-build/71/artifact/artifacts +Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allnoconfig-build/73/artifact/artifacts +Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allnoconfig-build/72/artifact/artifacts |