diff options
Diffstat (limited to 'notify/mail-body.txt')
| -rw-r--r-- | notify/mail-body.txt | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt index b6e9e78..acf3eb0 100644 --- a/notify/mail-body.txt +++ b/notify/mail-body.txt @@ -2,19 +2,25 @@ Dear contributor, our automatic CI has detected problems related to your patch(e In CI config tcwg_kernel/llvm-master-aarch64-lts-allyesconfig after: - | 354 commits in binutils,llvm - | 1e62d51f295 Automatic date update in version.in - | 8fbb497b720 gas: bpf: do not allow referring to register names as symbols in operands - | 26c7a0ea380 Automatic date update in version.in - | e5d6f72eb3d bpf: avoid creating wrong symbols while parsing - | 41336620315 gdb: pass address_space to target dcache functions - | ... and 38 more commits in binutils - | edad025d1e1f [clang-format] Correctly annotate braces of empty functions (#72733) - | cb3a605c5d45 [clang-format] Fix a bug in isStartOfName() on macro definitions (#72768) - | 5860d248a780 [clang-format] Fix a bug in aligning comments above PPDirective (#72791) - | e16a8344d0ef [clang-format][NFC] Skip alignArrayInitializers() for 1-row matrices (#72166) - | 797b68c0ba69 Revert "[MC][AsmParser] Diagnose improperly nested .cfi frames" - | ... and 306 more commits in llvm + | 582 commits in binutils,llvm,qemu + | 6e1d1b2e7b2 s390: Correct prno instruction name + | 2bf1f788bd7 s390: Add missing extended mnemonics + | fca086d928a s390: Align optional operand definition to specs + | eeafc61979c s390: Make operand table indices relative to each other + | 3f3c1e513bd s390: Add brasl edge test cases from ESA to z/Architecture + | ... and 63 more commits in binutils + | ba89749cd249 [libc++] <experimental/simd> Add implicit type conversion constructor for class simd/simd_mask (#71132) + | c4779ea8e709 [libc++abi] Avoid raw calls to assert() in libc++abi (#71121) + | 0a9c6bea6b08 [RISCV][GISel] Support G_CTTZ/CTLZ with Zbb. + | 96452676e534 [LAA] Factor out logic to compute dependence distance. (NFCI) + | 43bc81d7488a [mlir] fix LLVM type converter for structs (#73231) + | ... and 405 more commits in llvm + | b93c4313f2 Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging + | 2ebe6659ec Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa into staging + | 6bca4d7d1f target/riscv/cpu_helper.c: Fix mxr bit behavior + | 82d53adfbb target/riscv/cpu_helper.c: Invalid exception on MMU translation stage + | a7472560ca riscv: Fix SiFive E CLINT clock frequency + | ... and 99 more commits in qemu Results changed to # reset_artifacts: @@ -50,6 +56,6 @@ CI config tcwg_kernel/llvm-master-aarch64-lts-allyesconfig -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: -Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allyesconfig-build/106/artifact/artifacts -Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allyesconfig-build/105/artifact/artifacts +Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allyesconfig-build/107/artifact/artifacts +Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-lts-allyesconfig-build/106/artifact/artifacts |