diff options
| author | TCWG BuildSlave <tcwg-buildslave@linaro.org> | 2023-08-06 01:00:52 +0000 |
|---|---|---|
| committer | TCWG BuildSlave <tcwg-buildslave@linaro.org> | 2023-08-06 01:00:52 +0000 |
| commit | 56fa3554942767d0736c392bbc2236593e5fe857 (patch) | |
| tree | 4bf6bcbde43fa19cbf89c1d0d6f22ee6f295742d /notify/mail-body.txt | |
| parent | 04b9f4645b52f661bd03cbdbba375aab128bda37 (diff) | |
force: #75: boot: [TCWG CI] https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-stable-allmodconfig-build/75/
Results :
| # reset_artifacts:
| -10
| # build_abe binutils:
| -9
| # build_kernel_llvm:
| -5
| # build_abe qemu:
| -2
| # linux_n_obj:
| 32356
| # linux build successful:
| all
| # linux boot successful:
| boot
check_regression status : 0
Diffstat (limited to 'notify/mail-body.txt')
| -rw-r--r-- | notify/mail-body.txt | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt index 60b64b8..a9a0833 100644 --- a/notify/mail-body.txt +++ b/notify/mail-body.txt @@ -1,13 +1,13 @@ -[TCWG-CI] Success after qemu commit: 70 commits in qemu +[TCWG-CI] Success after llvm commit: 194 commits in llvm In CI config tcwg_kernel/llvm-master-arm-stable-allmodconfig after: - | qemu commits: - | 71934cf6bf878f82dac3fceb7d06d293ec3f6f8f Merge tag 'pull-ppc-20230804' of https://gitlab.com/danielhb/qemu into staging - | 0e2a3ec36885f6d79a96230f582d4455878c6373 target/ppc: Fix VRMA page size for ISA v3.0 - | 9915dac4847f3cc5ffd36e4c374a4eec83fe09b5 target/ppc: Fix pending HDEC when entering PM state - | 9201af096962a1967ce5d0b270ed16ae4edd3db6 target/ppc: Implement ASDR register for ISA v3.0 for HPT - | 6b6d4c1a0116c51098975131c16ecf7cefe68e79 ppc/pegasos2: Fix reg property of 64 bit BARs in device tree - | ... and 65 more + | llvm commits: + | ab202aa7004a451ee9f496505256cfcb94d71747 [Clang] Increase default architecture from sm_35 to sm_52 + | 54bda79335ba65b0ab739a97e24030fcd95165b7 AMDGPU: Simplify and improve sincos matching + | 660b740e4b3c4b23dfba36940ae0fe2ad41bfedf [DAG] Support store merging of vector constant stores + | 2ad297db2c0ea168822b4958dbe3f3c1d3198d79 [mlir][spirv] Handle zero-element tensors in spirv type conversion + | 7ef1718c4d4ecd99f3ba48236f7fd4fd9ffb540c [Driver] Don't try to spell check unsupported options + | ... and 189 more Results changed to # reset_artifacts: @@ -46,6 +46,6 @@ boot -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: -Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-stable-allmodconfig-build/74/artifact/artifacts -Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-stable-allmodconfig-build/72/artifact/artifacts +Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-stable-allmodconfig-build/75/artifact/artifacts +Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-stable-allmodconfig-build/74/artifact/artifacts |