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AgeCommit message (Expand)Author
2022-03-20LoongArch: Update ABI eflag in elf header.liuzhensong
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong
2022-03-18RISC-V: Cache management instructionsTsukasa OI
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI
2022-03-16binutils/readelf: handle AMDGPU relocation typesSimon Marchi
2022-03-16binutils/readelf: handle NT_AMDGPU_METADATA note nameSimon Marchi
2022-03-16binutils/readelf: decode AMDGPU-specific e_flagsSimon Marchi
2022-03-16binutils/readelf: handle AMDGPU OS ABIsSimon Marchi
2022-03-16bfd: add AMDGCN architectureSimon Marchi
2022-03-16Delete PowerPC macro insn supportAlan Modra
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra
2022-03-11gprofng: a new GNU profilerVladimir Mezentsev
2022-02-23RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu
2022-02-23RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI
2022-02-13PR28882, build failure with gcc-4.2 due to use of 0b literalsAlan Modra
2022-02-11gdb/fortran: support ptype and print commands for namelist variablesBhuvanendra Kumar N
2022-02-03Rename EM_56800V4 to EM_56800EF.Cary Coutant
2022-02-03Add new e_machine values.Cary Coutant
2022-01-25Fix a probem building the binutils on SPARC/amd64Klaus Ziegler
2022-01-22Add markers for 2.38 branchNick Clifton
2022-01-14PR28751 mbind2a / mbind2b regressions on powerpc*-linuxAlan Modra
2022-01-13Synchronize binutils libiberty sources with gcc version.Nick Clifton
2022-01-12ld: Initial DT_RELR supportH.J. Lu
2022-01-12gas: add visibility support for XCOFFClément Chigot
2022-01-05elf: Set p_align to the minimum page size if possibleH.J. Lu
2022-01-02Update year range in copyright notice of binutils filesAlan Modra
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu
2021-12-07Support AT_FXRNG and AT_KPRELOAD on FreeBSD.John Baldwin
2021-12-04sim: reorder header includesMike Frysinger
2021-12-02aarch64: Add BC instructionRichard Sandiford
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford
2021-12-02aarch64: Add support for +mopsRichard Sandiford
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford
2021-12-02gdb, include: replace pragmas with DIAGNOSTIC macros, fix build with g++ 4.8Simon Marchi
2021-12-01readelf: recognize FDO Packaging Metadata ELF noteLuca Boccassi
2021-12-01Fix the fields in the x_n union inside the the x_file structure so that point...Nick Clifton
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess
2021-11-23AArch64: Add support for AArch64 EFI (efi-*-aarch64).Tamar Christina
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus
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