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2022-05-19AArch64: Enable FP16 by default for Armv9-A.Tamar Christina
In Armv9-A SVE is mandatory, and for SVE FP16 is mandatory. This fixes a disconnect between GCC and binutils where GCC has FP16 on by default and gas doesn't. include/ChangeLog: 2022-05-16 Tamar Christina <tamar.christina@arm.com> * opcode/aarch64.h (AARCH64_ARCH_V9_FEATURES): Add AARCH64_FEATURE_F16. (cherry picked from commit e1e15284481896505eab0cbc556f2348ef8fffbf) Signed-off-by: Tamar Christina <tamar.christina@arm.com>
2022-04-13LoongArch: Update ABI eflag in elf header.Liuzhen Song
2022-02-14PR28882, build failure with gcc-4.2 due to use of 0b literalsAlan Modra
PR 28882 * elf/loongarch.h: Replace binary literals with hex. (cherry picked from commit ccbaaa36174c2c3184344ee0e6db648491149a33)
2022-02-09This is the 2.38 GNU Binutils releaseNick Clifton
2022-01-25Fix problem building binutils on SPARC/amd64Klaus Ziegler
PR 28816 * elf/common.h (AT_SUN_HWCAP): Make definition conditional.
2022-01-22Add markers for 2.38 branchNick Clifton
2022-01-14PR28751 mbind2a / mbind2b regressions on powerpc*-linuxAlan Modra
include/ * bfdlink.h (struct bfd_link_info): Add commonpagesize_is_set. ld/ PR 28751 * emultempl/elf.em (handle_option): Set commonpagesize_is_set. * ldelf.c (ldelf_after_parse): Don't error when only one of -z max-page-size or -z common-page-size is given, correct the other value to make it sane. * testsuite/ld-elf/elf.exp (mbind2a, mbind2b): Do not pass -z max-page-size.
2022-01-13Synchronize binutils libiberty sources with gcc version.Nick Clifton
+2021-12-30 Lancelot SIX <lsix@lancelotsix.com> + + * cp-demangle.c (d_clone_suffix): Support digits in clone tag + names. + * testsuite/demangle-expected: Check demangling of clone symbols + with digits in name. + +2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + Revert: + 2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-12-15 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-11-29 Eric Gallager <egallager@gcc.gnu.org> + + PR other/103021 + * Makefile.in: Use ETAGS variable in TAGS target. + * configure: Regenerate. + * configure.ac: Allow ETAGS variable to be overridden. + +2021-11-29 Andrew Pinski <apinski@marvell.com> + + * make-temp-file.c (try_dir): Check to see if the dir + is actually a directory. + +2021-10-22 Eric Gallager <egallager@gcc.gnu.org> + + PR other/102663 + * Makefile.in: Allow dvi-formatted documentation + to be installed. + +2021-10-17 Lu?s Ferreira <contact@lsferreira.net> + + PR d/102618 + * d-demangle.c (dlang_parse_qualified): Handle anonymous + symbols correctly. + * testsuite/d-demangle-expected: New tests to cover anonymous + symbols. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test case for function literals. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test cases for simple special + mangles. + +2021-10-12 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_parse_qualified): Remove redudant parenthesis + around lhs and rhs of assignments. + +2021-10-01 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add missing format for new test + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_Type): Validate MANGLED is nonnull. + * testsuite/d-demangle-expected: New test. + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_symbol_backref): Ensure strlen of + string is less than length computed by dlang_number. + +2021-09-01 Iain Sandoe <iain@sandoe.co.uk> * configure: Regenerate. + * configure.ac: Do not search for sbrk on Darwin. + * xmalloc.c: Do not declare sbrk unless it has been found + by configure. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_identifier): Skip over fake parent manglings. + * testsuite/d-demangle-expected: Add tests. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_parse_arrayliteral): Add 'info' parameter. + (dlang_parse_assocarray): Likewise. + (dlang_parse_structlit): Likewise. + (dlang_value): Likewise. Handle function literal symbols. + (dlang_template_args): Pass 'info' to dlang_value. + * testsuite/d-demangle-expected: Add new test. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_attributes): Handle typeof(*null). + (dlang_type): Likewise. Demangle 'n' as typeof(null). + * testsuite/d-demangle-expected: Update tests. + +2021-08-23 Iain Sandoe <iain@sandoe.co.uk> + + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Cast the first argument to set_32 as needed. -2021-07-03 Nick Clifton <nickc@redhat.com> +2021-08-18 Iain Sandoe <iain@sandoe.co.uk> + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Arrange to swap the LTO index tables where needed. # Please enter the commit message for your changes. Lines starting
2022-01-12ld: Initial DT_RELR supportH.J. Lu
Add a -z pack-relative-relocs option to enable DT_RELR and create a relr.dyn section for DT_RELR. DT_RELR is implemented with the linker relaxation infrastructure, but it doesn't require the --relax option enabled. -z pack-relative-relocs implies -z combreloc. -z nocombreloc implies -z nopack-relative-relocs. -z pack-relative-relocs is chosen over the similar option in lld, --pack-dyn-relocs=relr, to implement a glibc binary lockout mechanism with a special glibc version symbol, to avoid random crashes of DT_RELR binaries with the existing glibc binaries. bfd/ * elf-bfd.h (elf_link_hash_table): Add srelrdyn. * elflink.c (_bfd_elf_link_create_dynamic_sections): Create a .relr.dyn section for DT_RELR. include/ * bfdlink.h (bfd_link_info): Add enable_dt_relr. ld/ * News: Mention -z pack-relative-relocs and -z nopack-relative-relocs. * ld.texi: Document -z pack-relative-relocs and -z nopack-relative-relocs. * ldelf.c (ldelf_after_parse): Disable DT_RELR if not building PIE nor shared library. Add 3 spare dynamic tags for DT_RELR, DT_RELRSZ and DT_RELRENT. * ldlang.c (lang_relax_sections): Also enable relaxation if DT_RELR is enabled. * emulparams/elf32_x86_64.sh: Source dt-relr.sh. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/dt-relr.sh: New file. * scripttempl/elf.sc: Support .relr.dyn.
2022-01-12gas: add visibility support for XCOFFClément Chigot
XCOFF assembly defines the visibility using an additional argument on several pseudo-ops: .globl, .weak, .extern and .comm. This implies that .globl and .weak syntax is different than the usual GNU syntax. But we want to provide compatibility with AIX assembler, especially because GCC is generating the visibility using this XCOFF syntax. PR 22085 bfd/ChangeLog: * coffcode.h (coff_write_object_contents): Change XCOFF header vstamp field to 2. * coffgen.c (coff_print_symbol): Increase the size for n_type. gas/ChangeLog: * config/tc-ppc.c (ppc_xcoff_get_visibility): New function. (ppc_globl): New function. (ppc_weak): New function. (ppc_comm): Add visibility field support. (ppc_extern): Likewise. * testsuite/gas/all/cofftag.d: Adjust to new n_type size providing by objdump. * testsuite/gas/ppc/test1xcoff32.d: Likewise. * testsuite/gas/ppc/aix.exp: Add new tests. * testsuite/gas/ppc/xcoff-visibility-1-32.d: New test. * testsuite/gas/ppc/xcoff-visibility-1-64.d: New test. * testsuite/gas/ppc/xcoff-visibility-1.s: New test. include/ChangeLog: * coff/internal.h (SYM_V_INTERNAL, SYM_V_HIDDEN, SYM_V_PROTECTED, SYM_V_EXPORTED, SYM_V_MASK): New defines. * coff/xcoff.h (struct xcoff_link_hash_entry): Add visibility field. ld/ChangeLog: * testsuite/ld-pe/pr19803.d: Adjust to new n_type size providing by objdump.
2022-01-05elf: Set p_align to the minimum page size if possibleH.J. Lu
Currently, on 32-bit and 64-bit ARM, it seems that ld generates p_align values of 0x10000 even if no section alignment is greater than 0x1000. The issue is more general and probably affects other targets with multiple page sizes. While file layout absolutely must take 64K page size into account, that does not have to be reflected in the p_align value. If running on a 64K kernel, the file will be loaded at a 64K page boundary by necessity. On a 4K kernel, 64K alignment is not needed. The glibc loader has been fixed to honor p_align: https://sourceware.org/bugzilla/show_bug.cgi?id=28676 similar to kernel: commit ce81bb256a224259ab686742a6284930cbe4f1fa Author: Chris Kennelly <ckennelly@google.com> Date: Thu Oct 15 20:12:32 2020 -0700 fs/binfmt_elf: use PT_LOAD p_align values for suitable start address This means that on 4K kernels, we will start to do extra work for 64K p_align, but this pointless for pretty much all binaries (whose section alignment rarely exceeds 16). The minimum page size is used, instead of the maximum section alignment due to this glibc bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28688 It has been fixed in glibc 2.35. But linker output must work on existing glibc binaries. 1. Set p_align to the minimum page size while laying out segments aligning to the maximum page size or section alignment. The run-time loader can align segments to the minimum page size or above, depending on system page size. 2. If -z max-page-size=NNN is used, p_align will be set to the maximum page size or the largest section alignment. 3. If a section requires alignment higher than the minimum page size, don't set p_align to the minimum page size. 4. If a section requires alignment higher than the maximum page size, set p_align to the section alignment. 5. For objcopy, when the minimum page size != the maximum page size, p_align may be set to the minimum page size while segments are aligned to the maximum page size. In this case, the input p_align will be ignored and the maximum page size will be used to align the ouput segments. 6. Update linker to disallow the common page size > the maximum page size. 7. Update linker to avoid the common page size > the maximum page size. 8. Adjust pru_irq_map-1.d to expect p_align == sh_addralign: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 20000000 00007c 000004 00 AX 0 0 4 ... Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000074 0x00000000 0x00000000 0x00008 0x00008 RW 0x1 LOAD 0x00007c 0x20000000 0x20000000 0x00004 0x00004 R E 0x4 vs. Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 20000000 00007c 000004 00 AX 0 0 4 ... Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000074 0x00000000 0x00000000 0x00008 0x00008 RW 0x1 LOAD 0x00007c 0x20000000 0x20000000 0x00004 0x00004 R E 0x1 To enable this linker optimization, the backend should define ELF_P_ALIGN to ELF_MINPAGESIZE. bfd/ PR ld/28689 PR ld/28695 * elf-bfd.h (elf_backend_data): Add p_align. * elf.c (assign_file_positions_for_load_sections): Set p_align to the default p_align value while laying out segments aligning to maximum page size or section alignment. (elf_is_p_align_valid): New function. (copy_elf_program_header): Call elf_is_p_align_valid to determine if p_align is valid. * elfxx-target.h (ELF_P_ALIGN): New. Default to 0. (elfNN_bed): Add ELF_P_ALIGN. * elfxx-x86.h (ELF_P_ALIGN): New. Set to ELF_MINPAGESIZE. include/ PR ld/28689 PR ld/28695 * bfdlink.h (bfd_link_info): Add maxpagesize_is_set. ld/ PR ld/28689 PR ld/28695 * emultempl/elf.em (gld${EMULATION_NAME}_handle_option): Set link_info.maxpagesize_is_set for -z max-page-size=NNN. * ldelf.c (ldelf_after_parse): Disallow link_info.commonpagesize > link_info.maxpagesize. * testsuite/ld-elf/elf.exp: Pass -z max-page-size=0x4000 to linker to build mbind2a and mbind2b. * testsuite/ld-elf/header.d: Add -z common-page-size=0x100. * testsuite/ld-elf/linux-x86.exp: Add PR ld/28689 tests. * testsuite/ld-elf/p_align-1.c: New file. * testsuite/ld-elf/page-size-1.d: New test. * testsuite/ld-elf/pr26936.d: Add -z common-page-size=0x1000. * testsuite/ld-elf/seg.d: Likewise. * testsuite/ld-scripts/rgn-at5.d: Likewise. * testsuite/ld-pru/pru_irq_map-1.d: Append 1 to name. Adjust expected PT_LOAD segment alignment. * testsuite/ld-pru/pru_irq_map-2.d: Append 2 to name. * testsuite/ld-scripts/pr23571.d: Add -z max-page-size=0x1000.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker
This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta
This is the Hypervisor Extension 1.0 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, Note that following were added already as part of svinval extension support: HINVAL.GVMA, HINVAL.VVMA Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> bfd/ * cpu-riscv.c (riscv_priv_specs): Added entry for 1.12. * cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12. gas/ * config/tc-riscv.c (abort_version): Updated comment. (validate_riscv_insn): Annotate switch-break. * testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor. * testsuite/gas/riscv/h-ext-32.s: Likewise. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/h-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for hypervisor csrs and instrcutions. opcodes/ * riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta
This makes way for a clean 1.12 based Hypervisor Ext support. There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210 is based on priv spec 1.9.1, but it seems unlikely that they implemented H-ext). Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/csr-dw-regnums.d: Drop the hypervisor csrs defined in the privileged spec 1.9.1. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise. include/ * opcode/riscv-opc.h: Drop the hypervisor csrs defined in the privileged spec 1.9.1.
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford
This patch adds AArch32 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_2A and ARM_ARCH_V9_3A are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V9_1A, ARM_ARCH_V9_2A): New macros. (ARM_ARCH_V9_3A): Likewise. gas/ * doc/c-arm.texi: Add armv9.1-a, armv9.2-a and armv9.3-a. * config/tc-arm.c (armv91a_ext_table, armv92a_ext_table): New macros. (armv93a_ext_table): Likewise. (arm_archs): Add armv9.1-a, armv9.2-a and armv9.3-a. (cpu_arch_ver): Add ARM_ARCH_V9_1A, ARM_ARCH_V9_2A and ARM_ARCH_V9_3A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv9_1-a.d: New test. * testsuite/gas/arm/attr-march-armv9_2-a.d: Likewise. * testsuite/gas/arm/attr-march-armv9_3-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.1-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.2-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.3-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.1-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.2-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.3-a.d: Likewise.
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford
This patch adds AArch32 support for -march=armv8.[78]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros. gas/ * doc/c-arm.texi: Add armv8.7-a and armv8.8-a. * config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros. (arm_archs): Add armv8.7-a and armv8.8-a. (cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv8_7-a.d: New test. * testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford
This patch adds AArch64 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags, so we don't need to eat into the vanishing number of spare AARCH64_FEATURE_* bits. Hoewver, it was more convenient to separate out the |s of feature flags so that Armv9.1-A could reuse the set for Armv8.6-A, and so on. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8): ...here. (AARCH64_ARCH_V8_1_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_1): ...here. (AARCH64_ARCH_V8_2_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_2): ...here. (AARCH64_ARCH_V8_3_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_3): ...here. (AARCH64_ARCH_V8_4_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_4): ...here. (AARCH64_ARCH_V8_5_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_5): ...here. (AARCH64_ARCH_V8_6_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_6): ...here. (AARCH64_ARCH_V8_7_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_7): ...here. (AARCH64_ARCH_V8_8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_8): ...here. (AARCH64_ARCH_V9_FEATURES): New macro, split out from... (AARCH64_ARCH_V9): ...here. (AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros. (AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros. (AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros. gas/ * doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a. * config/tc-aarch64.c (aarch64_archs): Likewise. * NEWS: Mention the above. * testsuite/gas/aarch64/armv9_invalid.d, testsuite/gas/aarch64/armv9_invalid.s, testsuite/gas/aarch64/armv9_invalid.l: New test. * testsuite/gas/aarch64/armv9_1.d, testsuite/gas/aarch64/armv9_1.s: Likewise. * testsuite/gas/aarch64/armv9_1_invalid.d, testsuite/gas/aarch64/armv9_1_invalid.s, testsuite/gas/aarch64/armv9_1_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_2.d, testsuite/gas/aarch64/armv9_2.s: Likewise. * testsuite/gas/aarch64/armv9_2_invalid.d, testsuite/gas/aarch64/armv9_2_invalid.s, testsuite/gas/aarch64/armv9_2_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_3.d, testsuite/gas/aarch64/armv9_3.s: Likewise.
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu
According to the privileged spec, there are five new instructions for svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline for now, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0010011 rs2 rs1 000 00000 11100 11 hinval.gvma 0110011 rs2 rs1 000 00000 11100 11 This patch is cherry-picked from the riscv integration branch since the svinval extension is frozen for now. Besides, we fix the funct7 encodings of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011 and 0x0110011. bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. (riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL. gas/ * testsuite/gas/riscv/svinval.d: New testcase. * testsuite/gas/riscv/svinval.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for svinval. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_opcodes): Added svinval instructions.
2021-12-07Support AT_FXRNG and AT_KPRELOAD on FreeBSD.John Baldwin
FreeBSD's kernel has recently added two new ELF auxiliary vector entries. AT_FXRNG points to a root seed version for the kernel's PRNG. Userland can use this to reseed a userland PRNG after the kernel's PRNG has reseeded. AT_KPRELOAD is the base address of a kernel-provided vDSO. This change displays the proper name and description of these entries in 'info auxv'. include/ChangeLog: * elf/common.h (AT_FREEBSD_FXRNG, AT_FREEBSD_KPRELOAD): Define.
2021-12-04sim: reorder header includesMike Frysinger
We're including system headers after local headers in a bunch of places, but this leads to conflicts when our local headers happen to define symbols that show up in the system headers. Use the more standard order of: * config.h (via defs.h) * system headers * local library headers (e.g. bfd & libiberty) * sim specific headers
2021-12-02aarch64: Add BC instructionRichard Sandiford
This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford
The MOPS instructions should be used as a triple, such as: cpyfp [x0]!, [x1]!, x2! cpyfm [x0]!, [x1]!, x2! cpyfe [x0]!, [x1]!, x2! The registers should also be the same for each writeback operand. This patch adds a warning for code that doesn't follow this rule, along similar lines to the warning that we already emit for invalid uses of MOVPRFX. include/ * opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E) (C_SCAN_MOPS_PME): New macros. (AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind. (AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise. (aarch64_operand_error): Make each data value a union between an int and a string. opcodes/ * aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags. (MOPS_SET_OP1_OP2_INSN): Likewise. * aarch64-opc.c (set_out_of_range_error): Update after change to aarch64_operand_error. (set_unaligned_error, set_reg_list_error): Likewise. (init_insn_sequence): Use a 3-instruction sequence for MOPS P instructions. (verify_mops_pme_sequence): New function. (verify_constraints): Call it. * aarch64-dis.c (print_verifier_notes): Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. gas/ * config/tc-aarch64.c (operand_mismatch_kind_names): Add entries for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. (operand_error_higher_severity_p): Check that AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR; their relative order is not significant. (record_operand_error_with_data): Update after change to aarch64_operand_error. (output_operand_error_record): Likewise. Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. * testsuite/gas/aarch64/mops_invalid_2.s, testsuite/gas/aarch64/mops_invalid_2.d, testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02aarch64: Add support for +mopsRichard Sandiford
This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford
This patch adds skeleton support for -march=armv8.8-a, testing only that it correctly inherits from armv8.7-a. include/ * opcode/aarch64.h (AARCH64_FEATURE_V8_8): New macro. (AARCH64_ARCH_V8_8): Likewise. gas/ * doc/c-aarch64.texi: Document armv8.8-a. * config/tc-aarch64.c (aarch64_archs): Add armv8-8-a * testsuite/gas/aarch64/v8-8-a.s, * testsuite/gas/aarch64/v8-8-a.d: New test.
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford
libopcodes has some code to check constraints across sequences of consecutive instructions. It was added to support MOVPRFX sequences but is going to be useful for the Armv8.8-A MOPS feature as well. Currently the structure has one field to record the instruction that started a sequence and another to record the remaining instructions in the sequence. It's more convenient for the MOPS code if we put the instructions into a single array instead. No functional change intended. include/ * opcode/aarch64.h (aarch64_instr_sequence): Replace num_insns and current_insns with num_added_insns and num_allocated_insns. opcodes/ * aarch64-opc.c (add_insn_to_sequence): New function. (init_insn_sequence): Update for new aarch64_instr_sequence layout. Add the first instruction to the inst array. (verify_constraints): Update for new aarch64_instr_sequence layout. Don't add the last instruction to the array.
2021-12-02gdb, include: replace pragmas with DIAGNOSTIC macros, fix build with g++ 4.8Simon Marchi
When introducing this code, I forgot that we had some macros for this. Replace some "manual" pragma diagnostic with some DIAGNOSTIC_* macros, provided by include/diagnostics.h. In diagnostics.h: - Add DIAGNOSTIC_ERROR, to enable a diagnostic at error level. - Add DIAGNOSTIC_ERROR_SWITCH, to enable -Wswitch at error level, for both gcc and clang. Additionally, using DIAGNOSTIC_PUSH, DIAGNOSTIC_ERROR_SWITCH and DIAGNOSTIC_POP seems to misbehave with g++ 4.8, where we see these errors: CXX ada-tasks.o /home/smarchi/src/binutils-gdb/gdb/ada-tasks.c: In function void read_known_tasks(): /home/smarchi/src/binutils-gdb/gdb/ada-tasks.c:998:10: error: enumeration value ADA_TASKS_UNKNOWN not handled in switch [-Werror=switch] switch (data->known_tasks_kind) ^ Because of the POP, the diagnostic should go back to being disabled, since it was disabled in the beginning, but that's not what we see here. Versions of GCC >= 5 compile correctly. Work around this by making DIAGNOSTIC_ERROR_SWITCH a no-op for GCC < 5. Note that this code (already as it exists in master today) enables -Wswitch at the error level even if --disable-werror is passed. It shouldn't be a problem, as it's not like a new enumerator will appear out of nowhere and cause a build error if building with future compilers. Still, for correctness, we would ideally want to ask the compiler to enable -Wswitch at its default level (as if the user had passed -Wswitch on the command-line). There doesn't seem to be a way to do this. Change-Id: Id33ebec3de39bd449409ea0bab59831289ffe82d
2021-12-01readelf: recognize FDO Packaging Metadata ELF noteLuca Boccassi
As defined on: https://systemd.io/COREDUMP_PACKAGE_METADATA/ this note will be used starting from Fedora 36. Allow readelf --notes to pretty print it: Displaying notes found in: .note.package Owner Data size Description FDO 0x00000039 FDO_PACKAGING_METADATA Packaging Metadata: {"type":"deb","name":"fsverity-utils","version":"1.3-1"} Signed-off-by: Luca Boccassi <luca.boccassi@microsoft.com>
2021-12-01Fix the fields in the x_n union inside the the x_file structure so that ↵Nick Clifton
pointers can be stored. PR 28630 * coff/internal.h (x_n): Use bfd_hostptr_t for the fields in this structure.
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu
According the rvv spec, https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc The bits of vtype immediate from 8 to (xlen - 1) should be reserved. Therefore, we should also dump the vtype immediate as numbers, when they are set over 8-bits. I think this is a bug that we used to support vediv extension and use the bit 8 and 9 of vtype, but forgot to update the behavior when removing the vediv. Consider the testcases, vsetvli a0, a1, 0x700 # the reserved bit 10, 9 and 8 are used. vsetvli a0, a1, 0x400 # the reserved bit 10 is used. vsetvli a0, a1, 0x300 # the reserved bit 9 and 8 are used. vsetvli a0, a1, 0x100 # the reserved bit 8 is used. vsetivli a0, 0xb, 0x300 # the reserved bit 9 and 8 are used. vsetivli a0, 0xb, 0x100 # the reserved bit 8 is used. The original objdump shows the following result, 0000000000000000 <.text>: 0: 7005f557 vsetvli a0,a1,1792 4: 4005f557 vsetvli a0,a1,1024 8: 3005f557 vsetvli a0,a1,e8,m1,tu,mu c: 1005f557 vsetvli a0,a1,e8,m1,tu,mu 10: f005f557 vsetivli a0,11,e8,m1,tu,mu 14: d005f557 vsetivli a0,11,e8,m1,tu,mu But in fact the correct result should be, 0000000000000000 <.text>: 0: 7005f557 vsetvli a0,a1,1792 4: 4005f557 vsetvli a0,a1,1024 8: 3005f557 vsetvli a0,a1,768 c: 1005f557 vsetvli a0,a1,256 10: f005f557 vsetivli a0,11,768 14: d005f557 vsetivli a0,11,256 gas/ * testsuite/gas/riscv/vector-insns.d: Added testcases to test the reserved bit 8 to (xlen-1) of vtype. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv.h: Removed OP_MASK_VTYPE_RES and OP_SH_VTYPE_RES, since they are different for operand Vc and Vb. opcodes/ * riscv-dis.c (print_insn_args): Updated imm_vtype_res to extract the reserved immediate of vtype correctly.
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess
In preparation for the next commit, which will add GDB support for RISC-V disassembler options, this commit restructures how the disassembler options are managed within libopcodes. The implementation provided here is based on this mailing list patch which was never committed: https://sourceware.org/pipermail/binutils/2021-January/114944.html which in turn took inspiration from the MIPS implementation of the same feature. The biggest changes from the original mailing list post are: 1. The GDB changes have been split into a separate patch, and 2. The `riscv_option_args_privspec` variable, which held the valid priv-spec values is now gone, instead we use the `riscv_priv_specs` array from bfd/cpu-riscv.c instead. Co-authored-by: Simon Cook <simon.cook@embecosm.com> include/ChangeLog: * dis-asm.h (disassembler_options_riscv): Declare. opcodes/ChangeLog: * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. (riscv_options): New static global. (disassembler_options_riscv): New function. (print_riscv_disassembler_options): Rewrite to use disassembler_options_riscv.
2021-11-23AArch64: Add support for AArch64 EFI (efi-*-aarch64).Tamar Christina
This adds support for efi-*-aarch64 by virtue of adding a new PEI target pei-aarch64-little. This is not a full target and only exists to support EFI at this time. This means that this target does not support relocation processing and is mostly a container format. This format has been added to elf based aarch64 targets such that efi images can be made natively on Linux. However this target is not valid for use with gas but only with objcopy. With these changes the resulting file is recognized as an efi image by third party tools: > pecli info hello.efi Metadata ================================================================================ MD5: 598c32a778b0f0deebe977fef8578c4e SHA1: 4580121edd5cb4dc40f51b28f171fd15250df84c SHA256: 3154bd7cf42433d1c957f6bf55a17ad8c57ed41b29df2d485703349fd6ff1d5c Imphash: Size: 47561 bytes Type: PE32+ executable (EFI application) (stripped to external PDB), for MS Windows Compile Time: 1970-01-01 00:00:00 (UTC - 0x0 ) Entry point: 0x2000 (section .text) Sections ================================================================================ Name RWX VirtSize VirtAddr RawAddr RawSize Entropy md5 .text R-X 0x5bb0 0x2000 0x400 0x5c00 6.39 551fbc264256a3f387de8a891500ae0d .reloc R-- 0xc 0x8000 0x6000 0x200 0.02 0c45f6d812d079821c1d54c09ab89e1d .data RW- 0x1d88 0x9000 0x6200 0x1e00 4.18 5d1137c09f01289dc62bf754f7290db3 .dynamic RW- 0xf0 0xb000 0x8000 0x200 0.34 5c94ed3206f05a277e6f04fbf131f131 .rela R-- 0xe58 0xc000 0x8200 0x1000 1.87 8b5c6bc30f3acb7ca7bf2e6789d68519 .dynsym R-- 0x138 0xd000 0x9200 0x200 0.96 bdcf5101da51aadc663ca8859f88138c Imports ================================================================================ Any magic number is based on the Microsoft PE specification [1]. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format bfd/ChangeLog: 2021-10-21 Tamar Christina <tamar.christina@arm.com> PR binutils/26206 * .gitignore (pe-aarch64igen.c): New. * Makefile.am (pei-aarch64.lo, pe-aarch64igen.lo, pei-aarch64.c, pe-aarch64igen.c): Add support. * Makefile.in: Likewise. * bfd.c (bfd_get_sign_extend_vma): Add pei-aarch64-little. * coff-aarch64.c: New file. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags, coff_write_object_contents) Add aarch64 (aarch64_pei_vec) support. * config.bfd: Likewise. * configure: Likewise. * configure.ac: Likewise. * libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE, GET_OPTHDR_SIZE_OF_STACK_RESERVE, PUT_OPTHDR_SIZE_OF_STACK_RESERVE, GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT, GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE, GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT, GET_PDATA_ENTRY, _bfd_peAArch64_bfd_copy_private_bfd_data_common, _bfd_peAArch64_bfd_copy_private_section_data, _bfd_peAArch64_get_symbol_info, _bfd_peAArch64_only_swap_filehdr_out, _bfd_peAArch64_print_private_bfd_data_common, _bfd_peAArch64i_final_link_postscript, _bfd_peAArch64i_only_swap_filehdr_out, _bfd_peAArch64i_swap_aouthdr_in, _bfd_peAArch64i_swap_aouthdr_out, _bfd_peAArch64i_swap_aux_in, _bfd_peAArch64i_swap_aux_out, _bfd_peAArch64i_swap_lineno_in, _bfd_peAArch64i_swap_lineno_out, _bfd_peAArch64i_swap_scnhdr_out, _bfd_peAArch64i_swap_sym_in, _bfd_peAArch64i_swap_sym_out, _bfd_peAArch64i_swap_debugdir_in, _bfd_peAArch64i_swap_debugdir_out, _bfd_peAArch64i_write_codeview_record, _bfd_peAArch64i_slurp_codeview_record, _bfd_peAArch64_print_ce_compressed_pdata): New. * peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out, pe_print_pdata, _bfd_XX_print_private_bfd_data_common, _bfd_XX_bfd_copy_private_section_data, _bfd_XXi_final_link_postscript): Support COFF_WITH_peAArch64, * pei-aarch64.c: New file. * peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd, pe_ILF_object_p): Support COFF_WITH_peAArch64. (jtab): Add dummy entry that traps. * targets.c (aarch64_pei_vec): New. binutils/ChangeLog: 2021-10-21 Tamar Christina <tamar.christina@arm.com> PR binutils/26206 * NEWS: Add new support. * objcopy.c (convert_efi_target): Add efi-*-aarch64 support. * testsuite/binutils-all/aarch64/pei-aarch64-little.d: New test. * testsuite/binutils-all/aarch64/pei-aarch64-little.s: New test. include/ChangeLog: 2021-10-21 Tamar Christina <tamar.christina@arm.com> PR binutils/26206 * coff/aarch64.h: New file. * coff/pe.h (IMAGE_FILE_MACHINE_ARM64): New.
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu
This is the original discussion, https://github.com/riscv/riscv-elf-psabi-doc/pull/190 And here is the glibc part, https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html For binutils part, we need to support a new direcitve: .variant_cc. The function symbol marked by .variant_cc means it need to be resolved directly without resolver for dynamic linker. We also add a new dynamic entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the special attribute in the dynamic symbol table of the object. I heard that llvm already have supported this in their mainline, so I think it's time to commit this. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc flag. It is used to check if relocations for variant CC symbols may be present. (allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC flag, then raise the variant_cc flag of riscv_elf_link_hash_table. (riscv_elf_size_dynamic_sections): Added dynamic entry for variant_cc. (riscv_elf_merge_symbol_attribute): New function, used to merge non-visibility st_other attributes, including STO_RISCV_VARIANT_CC. binutils/ * readelf.c (get_riscv_dynamic_type): New function. (get_dynamic_type): Called get_riscv_dynamic_type for riscv targets. (get_riscv_symbol_other): New function. (get_symbol_other): Called get_riscv_symbol_other for riscv targets. gas/ * config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a variant CC convention. (riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes, but without copying st_other. If a function symbol has special st_other value set via directives, then attaching an IFUNC resolver to that symbol should not override the st_other setting. (riscv_pseudo_table): Support variant_cc diretive. * config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined. * testsuite/gas/riscv/variant_cc-set.d: New testcase. * testsuite/gas/riscv/variant_cc-set.s: Likewise. * testsuite/gas/riscv/variant_cc.d: Likewise. * testsuite/gas/riscv/variant_cc.s: Likewise. include/ * elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1). (STO_RISCV_VARIANT_CC): Defined to 0x80. ld/ * testsuite/ld-riscv-elf/variant_cc-1.s: New testcase. * testsuite/ld-riscv-elf/variant_cc-2.s: Likewise. * testsuite/ld-riscv-elf/variant_cc-now.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-r.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if z*inx enabled and use gpr instead of fpr when z*inx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for z*inx extension. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Added register choice for z*inx. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for z*inx. * riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus
This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus
This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus
This patch is adding new loads and stores defined by SME instructions. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_address): New parser. (parse_sme_za_hv_tiles_operand_with_braces): New parser. (parse_sme_za_array): New parser. (output_operand_error_record): Print error details if present. (parse_operands): Support new operands. * testsuite/gas/aarch64/sme-5-illegal.d: New test. * testsuite/gas/aarch64/sme-5-illegal.l: New test. * testsuite/gas/aarch64/sme-5-illegal.s: New test. * testsuite/gas/aarch64/sme-5.d: New test. * testsuite/gas/aarch64/sme-5.s: New test. * testsuite/gas/aarch64/sme-6-illegal.d: New test. * testsuite/gas/aarch64/sme-6-illegal.l: New test. * testsuite/gas/aarch64/sme-6-illegal.s: New test. * testsuite/gas/aarch64/sme-6.d: New test. * testsuite/gas/aarch64/sme-6.s: New test. * testsuite/gas/aarch64/sme-7-illegal.d: New test. * testsuite/gas/aarch64/sme-7-illegal.l: New test. * testsuite/gas/aarch64/sme-7-illegal.s: New test. * testsuite/gas/aarch64/sme-7.d: New test. * testsuite/gas/aarch64/sme-7.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands. (enum aarch64_insn_class): Added sme_ldr and sme_str. (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. (aarch64_ins_sme_za_list): New inserter. (aarch64_ins_sme_za_array): New inserter. (aarch64_ins_sme_addr_ri_u4xvl): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. (aarch64_ext_sme_za_list): New extractor. (aarch64_ext_sme_za_array): New extractor. (aarch64_ext_sme_addr_ri_u4xvl): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. * aarch64-opc.c (operand_general_constraint_met_p): (aarch64_match_operands_constraint): Handle sme_ldr, sme_str and sme_misc. (aarch64_print_operand): New operands supported. * aarch64-tbl.h (OP_SVE_QUU): New qualifier. (OP_SVE_QZU): New qualifier. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus
This patch is adding ZERO (a list of 64-bit element ZA tiles) instruction. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_list_of_64bit_tiles): New parser. (parse_operands): Handle OPND_SME_list_of_64bit_tiles. * testsuite/gas/aarch64/sme-4-illegal.d: New test. * testsuite/gas/aarch64/sme-4-illegal.l: New test. * testsuite/gas/aarch64/sme-4-illegal.s: New test. * testsuite/gas/aarch64/sme-4.d: New test. * testsuite/gas/aarch64/sme-4.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_list_of_64bit_tiles. opcodes/ChangeLog: * aarch64-opc.c (print_sme_za_list): New printing function. (aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles. * aarch64-opc.h (enum aarch64_field_kind): New bitfield FLD_SME_zero_mask. * aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus
This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus
Patch is adding new SME matrix instructions. Please note additional instructions will be added in following patches. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_zada_operand): New parser. * config/tc-aarch64.c (parse_reg_with_qual): New reg parser. * config/tc-aarch64.c (R_ZA): New egister type. (parse_operands): New parser. * testsuite/gas/aarch64/sme-illegal.d: New test. * testsuite/gas/aarch64/sme-illegal.l: New test. * testsuite/gas/aarch64/sme-illegal.s: New test. * testsuite/gas/aarch64/sme.d: New test. * testsuite/gas/aarch64/sme.s: New test. * testsuite/gas/aarch64/sme-f64.d: New test. * testsuite/gas/aarch64/sme-f64.s: New test. * testsuite/gas/aarch64/sme-i64.d: New test. * testsuite/gas/aarch64/sme-i64.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and AARCH64_OPND_SME_Pm. (enum aarch64_insn_class): New instruction class sme_misc. opcodes/ChangeLog: * aarch64-opc.c (aarch64_print_operand): Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands. (verify_constraints): Handle OPND_SME_Pm. * aarch64-opc.h (enum aarch64_field_kind): New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm. * aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set. (OP_SME_ZADA_PN_PM_ZN_D): New qualifier. (OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier. (OP_SME_ZADA_S_PM_PM_S_S): New qualifier. (OP_SME_ZADA_D_PM_PM_D_D): New qualifier. (OP_SME_ZADA_S_PM_PM_H_H): New qualifier. (OP_SME_ZADA_S_PM_PM_B_B): New qualifier. (OP_SME_ZADA_D_PM_PM_H_H): New qualifier. (SME_INSN): New instruction macro. (SME_F64_INSN): New instruction macro. (SME_I64_INSN): New instruction macro. (SME_INSNC): New instruction macro. (struct aarch64_opcode): New SME instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus
This series of patches (tagged [SME]) add support for the Scalable Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and +sme-i64 to -march command line options. gas/ChangeLog: * NEWS: Updated docs. * config/tc-aarch64.c: New SME command line options. * doc/c-aarch64.texi: Update docs. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_SME): New flag. (AARCH64_FEATURE_SME_F64): New flag. (AARCH64_FEATURE_SME_I64): New flag. opcodes/ChangeLog: * aarch64-tbl.h (SME): New feature object.
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu
2021-11-17 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector spec, https://github.com/riscv/riscv-v-spec bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules of v, zve and zvl extensions. (riscv_supported_std_ext): Updated verison of v to 1.0. (riscv_supported_std_z_ext): Added zve and zvl extensions. (riscv_parse_check_conflicts): The zvl extensions need to enable either v or zve extension. (riscv_multi_subset_supports): Check the subset list to know if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported. gas/ * config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V. (enum reg_class): Added RCLASS_VECR and RCLASS_VECM. (validate_riscv_insn): Check whether the rvv operands are valid. (md_begin): Initialize register hash for rvv registers. (macro_build): Added rvv operands when expanding rvv pseudoes. (vector_macro): Expand rvv macros into one or more instructions. (macro): Likewise. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_ip): Parse and encode rvv operands. Besides, The rvv loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march to rv32ifv_zkr. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/march-imply-v.d: New testcase. * testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/vector-insns.d: Likewise. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv. * opcode/riscv.h: Defined rvv immediate encodings and fields. (enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF. (INSN_V_EEW64): Defined. (M_VMSGE, M_VMSGEU): Added for the rvv pseudoes. opcodes/ * riscv-dis.c (print_insn_args): Dump the rvv operands. * riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers. (riscv_vecm_names_numeric): Likewise. (riscv_vsew): Likewise. (riscv_vlmul): Likewise. (riscv_vta): Likewise. (riscv_vma): Likewise. (match_vs1_eq_vs2): Added for rvv Vu operand. (match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand. (riscv_opcodes): Added rvv v1.0 instructions.
2021-11-16readelf: Support SHT_RELR/DT_RELR for -rFangrui Song
The -r output for SHT_RELR looks like: Relocation section '.relr.dyn' at offset 0x530 contains 4 entries: 7 offsets 00000000000028c0 00000000000028c8 0000000000003ad0 0000000000003ad8 0000000000003ae0 0000000000003ae8 0000000000003af0 For --use-dynamic, the header looks like 'RELR' relocation section at offset 0x530 contains 32 bytes: include/ * elf/common.h (DT_ENCODING): Bump to 38. * elf/external.h (Elf32_External_Relr): New. (Elf64_External_Relr): New. binutils/ * readelf.c (enum relocation_type): New. (slurp_relr_relocs): New. (dump_relocations): Change is_rela to rel_type. Dump RELR. (dynamic_relocations): Add DT_RELR. (process_relocs): Check SHT_RELR and DT_RELR. (process_dynamic_section): Store into dynamic_info for DT_RELR/DT_RELRENT/DT_RELRSZ.
2021-11-16sim: callback: expose argv & environMike Frysinger
Pass the existing strings data to the callbacks so that common libgloss syscalls can be implemented (which we'll do shortly).
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support. The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add a new Entropy Source CSR define 'seed' located at address 0x015. bfd/ * elfxx-riscv.c (riscv_multi_subset_supports): Added support for crypto extension. gas/ *config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR. (riscv_csr_address): Checked for CSR_CLASS_ZKR. (validate_riscv_insn): Added y and Y for bs and rnum operands. (riscv_ip): Handle y and Y operands. include/ * opcode/riscv-opc.h: Added encodings of crypto instructions. Also defined new csr seed, which address is 0x15. * opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto. opcodes/ * riscv-dis.c (print_insn_args): Recognized new y and Y operands. * riscv-opc.c (riscv_opcodes): Added crypto instructions.
2021-11-15PowerPC64 @notoc in non-power10 codeAlan Modra
R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on @notoc cals from non-power10 code in the rare case that using such a construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch instruction if power10 instructions are not enabled at that point. The new relocation tells the linker to not use power10 instructions on any stub emitted for that branch, unless overridden by --power10-stubs=yes. The current linker heuristic of only generating power10 instructions for stubs if power10-only relocations are detected, continues to be used. include/ * elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define. * elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc. (ppc64_elf_reloc_type_lookup): Handle it. (enum ppc_stub_type): Delete. (enum ppc_stub_main_type, ppc_stub_sub_type): New. (struct ppc_stub_type): New. (struct ppc_stub_hash_entry): Use the above new type. (struct ppc_link_hash_table): Update stub_count. (is_branch_reloc, ppc64_elf_check_relocs), (toc_adjusting_stub_needed): Handle new reloc. (stub_hash_newfunc, select_alt_stub, ppc_merge_stub), (ppc_type_of_stub, plt_stub_size, build_plt_stub), (build_tls_get_addr_head, build_tls_get_addr_tail), (ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs), (ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new reloc. Modify stub handling to suit new scheme. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc. (fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle BFD_RELOC_PPC64_REL24_P9NOTOC. ld/ * testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot
On XCOFF, ".file" pseudo-op allows 3 extras parameters to provide additional information to AIX linker, or its debugger. These are stored in auxiliary entries of the C_FILE symbol. bfd/ PR 28447 * coffcode.h (combined_entry_type): Add extrap field. (coff_bigobj_swap_aux_in): Adjust names of x_file fields. (coff_bigobj_swap_aux_out): Likewise. * coffgen.c (coff_write_auxent_fname): New function. (coff_fix_symbol_name): Write x_file using coff_write_auxent_fname. (coff_write_symbol): Likewise. (coff_write_symbols): Add C_FILE auxiliary entries to string table if needed. (coff_get_normalized_symtab): Adjust names of x_file fields. Normalize C_FILE auxiliary entries. (coff_print_symbol): Print C_FILE auxiliary entries. * coff-rs6000.c (_bfd_xcoff_swap_aux_in): Adjust names of x_file fields. (_bfd_xcoff_swap_aux_out): Likewise. * coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Likewise. (_bfd_xcoff64_swap_aux_out): Likewise. * cofflink.c (_bfd_coff_final_link): Likewise. (_bfd_coff_link_input_bfd): Likewise. * coffswap.h (coff_swap_aux_in): Likewise. * peXXigen.c (_bfd_XXi_swap_aux_in): Likewise. (_bfd_XXi_swap_aux_out): Likewise. * xcofflink.c (xcoff_link_input_bfd): Likewise. * libcoff.h: Regenerate. gas/ * config/tc-ppc.c (ppc_file): New function. * config/tc-ppc.h (OBJ_COFF_MAX_AUXENTRIES): Change to 4. * testsuite/gas/ppc/aix.exp: Add tests. * testsuite/gas/ppc/xcoff-file-32.d: New test. * testsuite/gas/ppc/xcoff-file-64.d: New test. * testsuite/gas/ppc/xcoff-file.s: New test. include/ * coff/internal.h (union internal_auxent): Change x_file to be a struct instead of a union. Add x_ftype field. * coff/rs6000.h (union external_auxent): Add x_resv field. * coff/xcoff.h (XFT_FN): New define. (XFT_CT): Likewise. (XFT_CV): Likewise. (XFT_CD): Likewise.
2021-11-06readelf: Support RELR in -S and -d and outputFangrui Song
readelf -r dumping support is not added in this patch. include/ * elf/common.h: Add SHT_RELR, DT_RELR{,SZ,ENT} bfd/ * elf.c (_bfd_elf_print_private_bfd_data): Add DT_RELR{,SZ,ENT}. binutils/ * readelf.c (get_dynamic_type): Add DT_RELR{,SZ,ENT}. (get_section_type_name): Add SHT_RELR.
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus
Update also include: + New value of Tag_CPU_arch EABI attribute (22) is added. + Updated missing Tag_CPU_arch EABI attributes. + Updated how we combine archs 'v4t_plus_v6_m' as this mechanism have to handle new Armv9 as well. Regression tested on `arm-none-eabi` cross Binutils and no issues. bfd/ * archures.c: Define bfd_mach_arm_9. * bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9. * cpu-arm.c: Add 'armv9-a' option to -march. * elf32-arm.c (using_thumb2_bl): Update assert check. (arch_has_arm_nop): Add TAG_CPU_ARCH_V9. (bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9. Update assert. (tag_cpu_arch_combine): Updated table. (v9): New table.. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Update with elfcpp/ * arm.h: Update TAG_CPU_ARCH_ enums with correct values. gas/ * NEWS: Update docs. * config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a for -amarch=all. (aeabi_set_public_attributes): Update assert. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/armv9-a_arch.d: New test. * testsuite/gas/arm/attr-march-all.d: Update test with v9. include/ * elf/arm.h Update TAG_CPU_ARCH_ defines with correct values. * opcode/arm.h (ARM_EXT3_V9A): New macro. (ARM_ARCH_NONE): Updated with arm_feature_set.core size. (FPU_NONE): Updated. (ARM_ANY): Updated. (ARM_ARCH_UNKNOWN): New macro. (ARM_FEATURE_LOW): Updated. (ARM_FEATURE_CORE): Updated. (ARM_FEATURE_CORE_LOW): Updated. (ARM_FEATURE_CORE_HIGH): Updated. (ARM_FEATURE_COPROC): Updated. (ARM_FEATURE): Updated. (ARM_FEATURE_ALL): New macro. opcodes/ * arm-dis.c (select_arm_features): Support bfd_mach_arm_9. Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
2021-10-24LoongArch opcodes supportliuzhensong
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> include/ * opcode/loongarch.h: New. * dis-asm.h: Declare print_loongarch_disassembler_options. opcodes/ * Makefile.am: Add LoongArch. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Declare print_insn_loongarch. * loongarch-coder.c: New. * loongarch-dis.c: New. * loongarch-opc.c: New. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
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