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AgeCommit message (Expand)Author
2022-05-19AArch64: Enable FP16 by default for Armv9-A.Tamar Christina
2022-04-13LoongArch: Update ABI eflag in elf header.Liuzhen Song
2022-02-14PR28882, build failure with gcc-4.2 due to use of 0b literalsAlan Modra
2022-02-09This is the 2.38 GNU Binutils releaseNick Clifton
2022-01-25Fix problem building binutils on SPARC/amd64Klaus Ziegler
2022-01-22Add markers for 2.38 branchNick Clifton
2022-01-14PR28751 mbind2a / mbind2b regressions on powerpc*-linuxAlan Modra
2022-01-13Synchronize binutils libiberty sources with gcc version.Nick Clifton
2022-01-12ld: Initial DT_RELR supportH.J. Lu
2022-01-12gas: add visibility support for XCOFFClément Chigot
2022-01-05elf: Set p_align to the minimum page size if possibleH.J. Lu
2022-01-02Update year range in copyright notice of binutils filesAlan Modra
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu
2021-12-07Support AT_FXRNG and AT_KPRELOAD on FreeBSD.John Baldwin
2021-12-04sim: reorder header includesMike Frysinger
2021-12-02aarch64: Add BC instructionRichard Sandiford
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford
2021-12-02aarch64: Add support for +mopsRichard Sandiford
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford
2021-12-02gdb, include: replace pragmas with DIAGNOSTIC macros, fix build with g++ 4.8Simon Marchi
2021-12-01readelf: recognize FDO Packaging Metadata ELF noteLuca Boccassi
2021-12-01Fix the fields in the x_n union inside the the x_file structure so that point...Nick Clifton
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess
2021-11-23AArch64: Add support for AArch64 EFI (efi-*-aarch64).Tamar Christina
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu
2021-11-16readelf: Support SHT_RELR/DT_RELR for -rFangrui Song
2021-11-16sim: callback: expose argv & environMike Frysinger
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei
2021-11-15PowerPC64 @notoc in non-power10 codeAlan Modra
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot
2021-11-06readelf: Support RELR in -S and -d and outputFangrui Song
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus
2021-10-24LoongArch opcodes supportliuzhensong
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