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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)Author
2021-03-29x86: move some opcode table entriesJan Beulich
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich
2021-03-25x86: fix AMD Zen3 insnsJan Beulich
2021-03-24x86: derive opcode length from opcode valueJan Beulich
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich
2021-03-03x86: infer operand count of templatesJan Beulich
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich
2021-02-16x86: have preprocessor expand macrosJan Beulich
2021-01-01Update year range in copyright notice of binutils filesAlan Modra
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian
2020-10-16Enhancement for avx-vnni patchCui,Lili
2020-10-14x86: Support Intel AVX VNNIH.J. Lu
2020-10-14x86: Add support for Intel HRESET instructionLili Cui
2020-10-14x86: Support Intel UINTRLili Cui
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu
2020-09-24Add support for Intel TDX instructions.Cui,Lili
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu
2020-07-10x86: Add support for Intel AMX instructionsLili Cui
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich
2020-07-02x86: Add SwapSourcesH.J. Lu
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili
2020-04-02Add support for intel SERIALIZE instructionLiliCui
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich
2020-03-09x86: allow opcode templates to be templatedJan Beulich
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich
2020-03-06x86: drop/replace IgnoreSizeJan Beulich
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich
2020-03-06x86: drop Rex64 attributeJan Beulich
2020-03-06x86: add missing IgnoreSizeJan Beulich
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich
2020-03-04x86: support VMGEXITJan Beulich
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu
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