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AgeCommit message (Expand)Author
2022-08-04Don't use BFD_VMA_FMT in binutilsAlan Modra
2022-08-03x86: properly mark i386-only insnsJan Beulich
2022-08-03x86: also use D for MOVBEJan Beulich
2022-08-02x86: XOP shift insns don't really allow B suffixJan Beulich
2022-08-01x86: SKINIT with operand needs IgnoreSizeJan Beulich
2022-08-01opcodes: LoongArch: add "ret" instruction to reduce typingWANG Xuerui
2022-08-01opcodes: LoongArch: make all non-native jumps desugar to canonical b{lt/ge}[u...WANG Xuerui
2022-08-01Get rid of fprintf_vma and sprintf_vmaAlan Modra
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess
2022-07-29x86: drop stray NoRex64 from KeyLocker insnsJan Beulich
2022-07-25libopcodes/ppc: add support for disassembler stylingAndrew Burgess
2022-07-25LoongArch:opcodes: Add new reloc types.liuzhensong
2022-07-21Add ChangeLog entry from previous commitPeter Bergner
2022-07-21PowerPC: Create new MMA instruction masks and use themPeter Bergner
2022-07-21x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich
2022-07-21x86/Intel: correct AVX512F scatter insn element sizesJan Beulich
2022-07-20Re: opcodes/arc: Implement style support in the disassemblerAlan Modra
2022-07-18opcodes/arc: Implement style support in the disassemblerClaudiu Zissulescu
2022-07-18x86: correct VMOVSH attributesJan Beulich
2022-07-18x86: re-order insn template fieldsJan Beulich
2022-07-09Regenerate with automake-1.15.1Alan Modra
2022-07-08libopcodes/s390: add support for disassembler stylingAndrew Burgess
2022-07-08Update version to 2.39.50 and regenerate filesNick Clifton
2022-07-08Add markers for 2.39 branchNick Clifton
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI
2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich
2022-07-04opcodes/avr: Implement style support in the disassemblerMarcus Nilsson
2022-07-04x86: fold Disp32S and Disp32Jan Beulich
2022-07-04x86: restore masking of displacement kindsJan Beulich
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess
2022-06-29x86: drop stray NoRex64 from XBEGINJan Beulich
2022-06-27drop XC16x bitsJan Beulich
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu
2022-06-15x86: drop print_operand_value()'s "hex" parameterJan Beulich
2022-06-13x86: fix incorrect indirectionJan Beulich
2022-06-13x86: replace global scratch bufferJan Beulich
2022-06-13x86: avoid string copy when swapping Vex.W controlled operandsJan Beulich
2022-06-13x86: shrink prefix related disassembler state fieldsJan Beulich
2022-06-13x86: properly initialize struct instr_info instance(s)Jan Beulich
2022-06-08libopcodes: extend the styling within the i386 disassemblerAndrew Burgess
2022-05-30RISC-V: Add zhinx extension supports.jiawei
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen
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