summaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)Author
2022-04-07IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel
2022-03-14PR28959, obdump doesn't disassemble mftb instructionAlan Modra
2022-02-17Updated Serbian translations for the bfd, gold, ld and opcodes directoriesNick Clifton
2022-02-09This is the 2.38 GNU Binutils releaseNick Clifton
2022-01-24Update Bulgarian, French, Romaniam and Ukranian translation for some of the s...Nick Clifton
2022-01-22CHange version number to 2.37.90 and regenerate filesNick Clifton
2022-01-22Add markers for 2.38 branchNick Clifton
2022-01-21drop old unused stamp-h.in fileMike Frysinger
2022-01-17Update the config.guess and config.sub files from the master repository and r...Nick Clifton
2022-01-17x86: adjust struct instr_info field typesJan Beulich
2022-01-17x86: drop index16 fieldJan Beulich
2022-01-17x86: drop most Intel syntax register name arraysJan Beulich
2022-01-17x86: fold variables in memory operand index handlingJan Beulich
2022-01-17x86: constify disassembler static dataJan Beulich
2022-01-14x86: drop ymmxmm_modeJan Beulich
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich
2022-01-14x86: record further wrong uses of EVEX.bJan Beulich
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford
2022-01-06x86: drop NoAVX insn attributeJan Beulich
2022-01-06x86: drop NoAVX from POPCNTJan Beulich
2022-01-06x86: drop some "comm" template parametersJan Beulich
2022-01-06x86: templatize FMA insn templatesJan Beulich
2022-01-05opcodes: Make i386-dis.c thread-safeVladimir Mezentsev
2022-01-02Update year range in copyright notice of binutils filesAlan Modra
2022-01-01unify 64-bit bfd checksMike Frysinger
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford
2021-12-03Revert "Re: Don't compile some opcodes files when bfd is 32-bit only"Alan Modra
2021-12-02aarch64: Add BC instructionRichard Sandiford
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford
2021-12-02aarch64: Add support for +mopsRichard Sandiford
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford
2021-12-02Allow the --visualize-jumps feature to work with the AVR disassembler.Marcus Nilsson
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu
2021-11-29opcodes: enable silent build rulesMike Frysinger
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 22:55:48 +0000