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path: root/sim/example-synacor
AgeCommit message (Expand)Author
2021-05-16sim: riscv: move __int128 check to configureMike Frysinger
2021-05-14sim: create header namespaceMike Frysinger
2021-05-04sim: add support for build-time ar & ranlibMike Frysinger
2021-05-01sim: nrun: add local strsignal prototypeMike Frysinger
2021-04-26sim: enable hardware support by defaultMike Frysinger
2021-04-22Do not check for sys/time.h or sys/times.hTom Tromey
2021-04-22Require GNU makeTom Tromey
2021-04-21sim: regen against sim/m4/Mike Frysinger
2021-04-21sim: use -Werror when probing for supported warning flagsSimon Marchi
2021-04-18sim: switch to AC_CHECK_HEADERS_ONCEMike Frysinger
2021-04-18sim: switch to AC_CHECK_FUNCS_ONCE & merge a littleMike Frysinger
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger
2021-04-03sim: example-synacor: a simple implementation for referenceMike Frysinger