[llvm-mca] Move field 'AllowZeroMoveEliminationOnly' to class RegisterFile. NFC.

Flag 'AllowZeroMoveEliminationOnly' should have been a property of the PRF, and
not set at register granularity.

This change also restricts move elimination to writes that update a full
physical register. We assume that there is a strong correlation between
logical registers that allow move elimination, and how those same registers are
allocated to physical registers by the register renamer.

This is still a no functional change, because this experimental code path is
disabled for now. This is done in preparation for another patch that will add
the ability to describe how move elimination works in scheduling models.

2 files changed, 23 insertions, 5 deletions

diff --git a/llvm/tools/llvm-mca/include/HardwareUnits/RegisterFile.h b/llvm/tools/llvm-mca/include/HardwareUnits/RegisterFile.h
index 1fa4642dac4..1026079c377 100644
--- a/llvm/tools/llvm-mca/include/HardwareUnits/RegisterFile.h
+++ b/llvm/tools/llvm-mca/include/HardwareUnits/RegisterFile.h
@@ -64,6 +64,9 @@ class RegisterFile : public HardwareUnit {
     // NumMoveEliminated is less than MaxMoveEliminatedPerCycle.
     unsigned NumMoveEliminated;
 
+    // If set, move elimination is restricted to zero-register moves only.
+    bool AllowZeroMoveEliminationOnly;
+
     RegisterMappingTracker(unsigned NumPhysRegisters,
                            unsigned MaxMoveEliminated = 0U)
         : NumPhysRegs(NumPhysRegisters), NumUsedPhysRegs(0),
@@ -104,16 +107,13 @@ class RegisterFile : public HardwareUnit {
   //
   // Field `AllowMoveElimination` is set for registers that are used as
   // destination by optimizable register moves.
-  // Field `AllowZeroMoveEliminationOnly` further restricts move elimination
-  // only to zero-register moves.
   struct RegisterRenamingInfo {
     IndexPlusCostPairTy IndexPlusCost;
     llvm::MCPhysReg RenameAs;
     bool AllowMoveElimination;
-    bool AllowZeroMoveEliminationOnly;
     RegisterRenamingInfo()
         : IndexPlusCost(std::make_pair(0U, 1U)), RenameAs(0U),
-          AllowMoveElimination(false), AllowZeroMoveEliminationOnly(false) {}
+          AllowMoveElimination(false) {}
   };
 
   // RegisterMapping objects are mainly used to track physical register
diff --git a/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp b/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
index 3ab1b5639ca..51a24786139 100644
--- a/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
+++ b/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
@@ -284,13 +284,31 @@ bool RegisterFile::tryEliminateMove(WriteState &WS, const ReadState &RS) {
   if (RegisterFileIndex != RRITo.IndexPlusCost.first)
     return false;
 
+  // We only allow move elimination for writes that update a full physical
+  // register. On X86, move elimination is possible with 32-bit general purpose
+  // registers because writes to those registers are not partial writes.  If a
+  // register move is a partial write, then we conservatively assume that move
+  // elimination fails, since it would either trigger a partial update, or the
+  // issue of a merge opcode.
+  //
+  // Note that this constraint may be lifted in future.  For example, we could
+  // make this model more flexible, and let users customize the set of registers
+  // (i.e. register classes) that allow move elimination.
+  //
+  // For now, we assume that there is a strong correlation between registers
+  // that allow move elimination, and how those same registers are renamed in
+  // hardware.
+  if (RRITo.RenameAs && RRITo.RenameAs != WS.getRegisterID())
+    if (!WS.clearsSuperRegisters())
+      return false;
+
   RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex];
   if (RMT.MaxMoveEliminatedPerCycle &&
       RMT.NumMoveEliminated == RMT.MaxMoveEliminatedPerCycle)
     return false;
 
   bool IsZeroMove = ZeroRegisters[RS.getRegisterID()];
-  if (RRITo.AllowZeroMoveEliminationOnly && !IsZeroMove)
+  if (RMT.AllowZeroMoveEliminationOnly && !IsZeroMove)
     return false;
 
   RMT.NumMoveEliminated++;