diff options
author | Craig Topper <craig.topper@intel.com> | 2019-01-16 00:20:30 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@intel.com> | 2019-01-16 00:20:30 +0000 |
commit | ce532d0590c0e2e6fedef99bc6b0387e432b01eb (patch) | |
tree | f88ea2f91ba17d1e1832313bbbfbcb93e646931e | |
parent | 6af9924cfdbfe3324a82df14baed532081ebf249 (diff) |
[X86] Rename SHRUNKBLEND ISD node to BLENDV.
That's really what it is. If we didn't use intrinsics for BLENDVPS/BLENDVPD/PBLENDVB all the way to isel, this is the node we would use.
-rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 | ||||
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 22 | ||||
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.h | 5 |
3 files changed, 16 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 130a6134b23..5ac153244df 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -3381,8 +3381,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) { } break; - case X86ISD::SHRUNKBLEND: { - // SHRUNKBLEND selects like a regular VSELECT. Same with X86ISD::SELECT. + case X86ISD::BLENDV: { + // BLENDV selects like a regular VSELECT. SDValue VSelect = CurDAG->getNode( ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0), Node->getOperand(1), Node->getOperand(2)); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1d99f097dc7..23d74ec2d3b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23582,7 +23582,7 @@ static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget, SDValue Src = Op.getOperand(0); SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Src); - return DAG.getNode(X86ISD::SHRUNKBLEND, DL, VT, Src, Sub, Src); + return DAG.getNode(X86ISD::BLENDV, DL, VT, Src, Sub, Src); } if (VT.is256BitVector() && !Subtarget.hasInt256()) { @@ -27132,7 +27132,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; case X86ISD::ANDNP: return "X86ISD::ANDNP"; case X86ISD::BLENDI: return "X86ISD::BLENDI"; - case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND"; + case X86ISD::BLENDV: return "X86ISD::BLENDV"; case X86ISD::HADD: return "X86ISD::HADD"; case X86ISD::HSUB: return "X86ISD::HSUB"; case X86ISD::FHADD: return "X86ISD::FHADD"; @@ -33974,13 +33974,13 @@ static SDValue combineSelectOfTwoConstants(SDNode *N, SelectionDAG &DAG) { /// this node with one of the variable blend instructions, restructure the /// condition so that blends can use the high (sign) bit of each element. /// This function will also call SimplfiyDemandedBits on already created -/// SHRUNKBLENDS to perform additional simplifications. -static SDValue combineVSelectToShrunkBlend(SDNode *N, SelectionDAG &DAG, +/// BLENDV to perform additional simplifications. +static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { SDValue Cond = N->getOperand(0); if ((N->getOpcode() != ISD::VSELECT && - N->getOpcode() != X86ISD::SHRUNKBLEND) || + N->getOpcode() != X86ISD::BLENDV) || ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) return SDValue(); @@ -34023,7 +34023,7 @@ static SDValue combineVSelectToShrunkBlend(SDNode *N, SelectionDAG &DAG, for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end(); UI != UE; ++UI) if ((UI->getOpcode() != ISD::VSELECT && - UI->getOpcode() != X86ISD::SHRUNKBLEND) || + UI->getOpcode() != X86ISD::BLENDV) || UI.getOperandNo() != 0) return SDValue(); @@ -34040,10 +34040,10 @@ static SDValue combineVSelectToShrunkBlend(SDNode *N, SelectionDAG &DAG, // optimizations as we messed with the actual expectation for the vector // boolean values. for (SDNode *U : Cond->uses()) { - if (U->getOpcode() == X86ISD::SHRUNKBLEND) + if (U->getOpcode() == X86ISD::BLENDV) continue; - SDValue SB = DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(U), U->getValueType(0), + SDValue SB = DAG.getNode(X86ISD::BLENDV, SDLoc(U), U->getValueType(0), Cond, U->getOperand(1), U->getOperand(2)); DAG.ReplaceAllUsesOfValueWith(SDValue(U, 0), SB); DCI.AddToWorklist(U); @@ -34062,7 +34062,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, SDValue RHS = N->getOperand(2); // Try simplification again because we use this function to optimize - // SHRUNKBLEND nodes that are not handled by the generic combiner. + // BLENDV nodes that are not handled by the generic combiner. if (SDValue V = DAG.simplifySelect(Cond, LHS, RHS)) return V; @@ -34429,7 +34429,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DCI, Subtarget)) return V; - if (SDValue V = combineVSelectToShrunkBlend(N, DAG, DCI, Subtarget)) + if (SDValue V = combineVSelectToBLENDV(N, DAG, DCI, Subtarget)) return V; // Custom action for SELECT MMX @@ -41500,7 +41500,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, return combineExtractSubvector(N, DAG, DCI, Subtarget); case ISD::VSELECT: case ISD::SELECT: - case X86ISD::SHRUNKBLEND: return combineSelect(N, DAG, DCI, Subtarget); + case X86ISD::BLENDV: return combineSelect(N, DAG, DCI, Subtarget); case ISD::BITCAST: return combineBitcast(N, DAG, DCI, Subtarget); case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget); case X86ISD::CMP: return combineCMP(N, DAG); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 4866cb2b82a..910acd80e8b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -203,8 +203,9 @@ namespace llvm { /// Dynamic (non-constant condition) vector blend where only the sign bits /// of the condition elements are used. This is used to enforce that the - /// condition mask is not valid for generic VSELECT optimizations. - SHRUNKBLEND, + /// condition mask is not valid for generic VSELECT optimizations. This + /// can also be used to implement the intrinsics. + BLENDV, /// Combined add and sub on an FP vector. ADDSUB, |