diff options
author | Oliver Stannard <oliver.stannard@arm.com> | 2018-10-02 09:48:43 +0000 |
---|---|---|
committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-10-02 09:48:43 +0000 |
commit | 07f7c6f23df4f76de45606b1534d2e5bad2c35e9 (patch) | |
tree | 9d0139ecc401f172432b04fd73206e798e1d2a50 | |
parent | 6cb442849ec031d9495b631ea13df410d83f7c6e (diff) |
[AArch64][v8.5A] Add MTE system instructions
The Memory Tagging Extension adds system instructions for data cache
maintenance, implemented as new operands to the DC instruction.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52487
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 21 | ||||
-rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 1 | ||||
-rw-r--r-- | llvm/test/MC/AArch64/armv8.5a-mte.s | 60 | ||||
-rw-r--r-- | llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt | 60 |
4 files changed, 142 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index fe8c797b216..240b46ef10c 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -108,6 +108,27 @@ def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>; +let Requires = [{ {AArch64::FeatureMTE} }] in { +def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>; +def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>; +def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>; +def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; +def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>; +def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>; +def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>; +def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; +def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>; +def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>; +def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>; +def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>; +def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; +def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>; +def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>; +def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>; +def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; +def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; +} + //===----------------------------------------------------------------------===// // IC (instruction cache maintenance) instruction options. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index d3b6c0d606a..55bc361b4c4 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2825,6 +2825,7 @@ static const struct Extension { { "lse", {AArch64::FeatureLSE} }, { "predctrl", {AArch64::FeaturePredCtrl} }, { "ccdp", {AArch64::FeatureCacheDeepPersist} }, + { "mte", {AArch64::FeatureMTE} }, // FIXME: Unsupported extensions { "pan", {} }, diff --git a/llvm/test/MC/AArch64/armv8.5a-mte.s b/llvm/test/MC/AArch64/armv8.5a-mte.s new file mode 100644 index 00000000000..345797a11d0 --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.5a-mte.s @@ -0,0 +1,60 @@ +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMTE +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-mte < %s 2>&1 | FileCheck %s --check-prefix=NOMTE + +dc igvac, x0 +dc igsw, x1 +dc cgsw, x2 +dc cigsw, x3 +dc cgvac, x4 +dc cgvap, x5 +dc cgvadp, x6 +dc cigvac, x7 +dc gva, x8 +dc igdvac, x9 +dc igdsw, x10 +dc cgdsw, x11 +dc cigdsw, x12 +dc cgdvac, x13 +dc cgdvap, x14 +dc cgdvadp, x15 +dc cigdvac, x16 +dc gzva, x17 + +// CHECK: dc igvac, x0 // encoding: [0x60,0x76,0x08,0xd5] +// CHECK: dc igsw, x1 // encoding: [0x81,0x76,0x08,0xd5] +// CHECK: dc cgsw, x2 // encoding: [0x82,0x7a,0x08,0xd5] +// CHECK: dc cigsw, x3 // encoding: [0x83,0x7e,0x08,0xd5] +// CHECK: dc cgvac, x4 // encoding: [0x64,0x7a,0x0b,0xd5] +// CHECK: dc cgvap, x5 // encoding: [0x65,0x7c,0x0b,0xd5] +// CHECK: dc cgvadp, x6 // encoding: [0x66,0x7d,0x0b,0xd5] +// CHECK: dc cigvac, x7 // encoding: [0x67,0x7e,0x0b,0xd5] +// CHECK: dc gva, x8 // encoding: [0x68,0x74,0x0b,0xd5] +// CHECK: dc igdvac, x9 // encoding: [0xa9,0x76,0x08,0xd5] +// CHECK: dc igdsw, x10 // encoding: [0xca,0x76,0x08,0xd5] +// CHECK: dc cgdsw, x11 // encoding: [0xcb,0x7a,0x08,0xd5] +// CHECK: dc cigdsw, x12 // encoding: [0xcc,0x7e,0x08,0xd5] +// CHECK: dc cgdvac, x13 // encoding: [0xad,0x7a,0x0b,0xd5] +// CHECK: dc cgdvap, x14 // encoding: [0xae,0x7c,0x0b,0xd5] +// CHECK: dc cgdvadp, x15 // encoding: [0xaf,0x7d,0x0b,0xd5] +// CHECK: dc cigdvac, x16 // encoding: [0xb0,0x7e,0x0b,0xd5] +// CHECK: dc gzva, x17 // encoding: [0x91,0x74,0x0b,0xd5] + +// NOMTE: DC IGVAC requires mte +// NOMTE: DC IGSW requires mte +// NOMTE: DC CGSW requires mte +// NOMTE: DC CIGSW requires mte +// NOMTE: DC CGVAC requires mte +// NOMTE: DC CGVAP requires mte +// NOMTE: DC CGVADP requires mte +// NOMTE: DC CIGVAC requires mte +// NOMTE: DC GVA requires mte +// NOMTE: DC IGDVAC requires mte +// NOMTE: DC IGDSW requires mte +// NOMTE: DC CGDSW requires mte +// NOMTE: DC CIGDSW requires mte +// NOMTE: DC CGDVAC requires mte +// NOMTE: DC CGDVAP requires mte +// NOMTE: DC CGDVADP requires mte +// NOMTE: DC CIGDVAC requires mte +// NOMTE: DC GZVA requires mte diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt new file mode 100644 index 00000000000..1b2cd1814a7 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt @@ -0,0 +1,60 @@ +# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOMTE +# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE + +[0x60,0x76,0x08,0xd5] +[0x81,0x76,0x08,0xd5] +[0x82,0x7a,0x08,0xd5] +[0x83,0x7e,0x08,0xd5] +[0x64,0x7a,0x0b,0xd5] +[0x65,0x7c,0x0b,0xd5] +[0x66,0x7d,0x0b,0xd5] +[0x67,0x7e,0x0b,0xd5] +[0x68,0x74,0x0b,0xd5] +[0xa9,0x76,0x08,0xd5] +[0xca,0x76,0x08,0xd5] +[0xcb,0x7a,0x08,0xd5] +[0xcc,0x7e,0x08,0xd5] +[0xad,0x7a,0x0b,0xd5] +[0xae,0x7c,0x0b,0xd5] +[0xaf,0x7d,0x0b,0xd5] +[0xb0,0x7e,0x0b,0xd5] +[0x91,0x74,0x0b,0xd5] + +# CHECK: dc igvac, x0 +# CHECK: dc igsw, x1 +# CHECK: dc cgsw, x2 +# CHECK: dc cigsw, x3 +# CHECK: dc cgvac, x4 +# CHECK: dc cgvap, x5 +# CHECK: dc cgvadp, x6 +# CHECK: dc cigvac, x7 +# CHECK: dc gva, x8 +# CHECK: dc igdvac, x9 +# CHECK: dc igdsw, x10 +# CHECK: dc cgdsw, x11 +# CHECK: dc cigdsw, x12 +# CHECK: dc cgdvac, x13 +# CHECK: dc cgdvap, x14 +# CHECK: dc cgdvadp, x15 +# CHECK: dc cigdvac, x16 +# CHECK: dc gzva, x17 + +# NOMTE: sys #0, c7, c6, #3, x0 +# NOMTE: sys #0, c7, c6, #4, x1 +# NOMTE: sys #0, c7, c10, #4, x2 +# NOMTE: sys #0, c7, c14, #4, x3 +# NOMTE: sys #3, c7, c10, #3, x4 +# NOMTE: sys #3, c7, c12, #3, x5 +# NOMTE: sys #3, c7, c13, #3, x6 +# NOMTE: sys #3, c7, c14, #3, x7 +# NOMTE: sys #3, c7, c4, #3, x8 +# NOMTE: sys #0, c7, c6, #5, x9 +# NOMTE: sys #0, c7, c6, #6, x10 +# NOMTE: sys #0, c7, c10, #6, x11 +# NOMTE: sys #0, c7, c14, #6, x12 +# NOMTE: sys #3, c7, c10, #5, x13 +# NOMTE: sys #3, c7, c12, #5, x14 +# NOMTE: sys #3, c7, c13, #5, x15 +# NOMTE: sys #3, c7, c14, #5, x16 +# NOMTE: sys #3, c7, c4, #4, x17 |