diff options
| author | Kang Zhang <shkzhang@cn.ibm.com> | 2018-12-25 03:29:51 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2018-12-25 03:29:51 +0000 |
| commit | 9181cfa61f7f9b6f59fac04b6cd893f12dba58e2 (patch) | |
| tree | 716d8fad8a050cb9a3559cb4209c7eeb558ebc06 | |
| parent | bf4e986887593d329fa5053203bd8fabb0d15e6b (diff) | |
[PowerPC] Fix the bug of ISD::ADDE to set its second return type to glue
Summary:
This patch is to fix the bug imported by rL341634.
In above submit , the the return type of ISD::ADDE is
14224: SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64),
but in fact, the second return type of ISD::ADDE should be
MVT::Glue not MVT::i64.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D55977
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/adde_return_type.ll | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a1c2e2f74ee..fed73639ce6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14389,7 +14389,7 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG, return SDValue(); SDLoc DL(N); - SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64); + SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue); SDValue Cmp = RHS.getOperand(0); SDValue Z = Cmp.getOperand(0); auto *Constant = dyn_cast<ConstantSDNode>(Cmp.getOperand(1)); diff --git a/llvm/test/CodeGen/PowerPC/adde_return_type.ll b/llvm/test/CodeGen/PowerPC/adde_return_type.ll new file mode 100644 index 00000000000..7ce11079a62 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/adde_return_type.ll @@ -0,0 +1,11 @@ +; REQUIRES: asserts +; RUN: llc -mtriple=powerpc64le-unknown-unknown -debug-only=legalize-types \ +; RUN: < %s -o /dev/null 2>&1 | FileCheck %s + +define i64 @testAddeReturnType(i64 %X, i64 %Z) { +; CHECK: Legally typed node: {{.*}}: i64,glue = adde {{.*}} + %cmp = icmp ne i64 %Z, 0 + %conv1 = zext i1 %cmp to i64 + %add = add nsw i64 %conv1, %X + ret i64 %add +} |