diff options
| author | Ryan Prichard <rprichard@google.com> | 2018-09-26 20:50:38 +0000 |
|---|---|---|
| committer | Ryan Prichard <rprichard@google.com> | 2018-09-26 20:50:38 +0000 |
| commit | 6869b49daf18db258b6ec21f34081ff66cb64b8d (patch) | |
| tree | a745e3754f553ebaf272688c5a7ecb513a42727a /lld | |
| parent | 0df9458c3b3402447852ca3907570cc231660225 (diff) | |
[AArch64] Fix range check of R_AARCH64_TLSLE_ADD_TPREL_HI12
Summary:
An AArch64 LE relocation is a positive ("variant 1") offset. This
relocation is used to write the upper 12 bits of a 24-bit offset into an
add instruction:
add x0, x0, :tprel_hi12:v1
The comment in the ARM docs for R_AARCH64_TLSLE_ADD_TPREL_HI12 is:
"Set an ADD immediate field to bits [23:12] of X; check 0 <= X < 2^24."
Reviewers: javed.absar, espindola, ruiu, peter.smith, zatrazz
Reviewed By: ruiu
Subscribers: emaste, arichardson, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D52525
Diffstat (limited to 'lld')
| -rw-r--r-- | lld/ELF/Arch/AArch64.cpp | 2 | ||||
| -rw-r--r-- | lld/test/ELF/aarch64-tls-le.s | 19 |
2 files changed, 19 insertions, 2 deletions
diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 7a0d28ed56b..be7710979d4 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -346,7 +346,7 @@ void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { or32le(Loc, (Val & 0xFFFC) << 3); break; case R_AARCH64_TLSLE_ADD_TPREL_HI12: - checkInt(Loc, Val, 24, Type); + checkUInt(Loc, Val, 24, Type); or32AArch64Imm(Loc, Val >> 12); break; case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: diff --git a/lld/test/ELF/aarch64-tls-le.s b/lld/test/ELF/aarch64-tls-le.s index a77068dca90..85cd3beac9e 100644 --- a/lld/test/ELF/aarch64-tls-le.s +++ b/lld/test/ELF/aarch64-tls-le.s @@ -13,6 +13,9 @@ _start: mrs x0, TPIDR_EL0 add x0, x0, :tprel_hi12:v1 add x0, x0, :tprel_lo12_nc:v1 + mrs x0, TPIDR_EL0 + add x0, x0, :tprel_hi12:v2 + add x0, x0, :tprel_lo12_nc:v2 # TCB size = 0x16 and foo is first element from TLS register. #CHECK: Disassembly of section .text: @@ -20,12 +23,26 @@ _start: #CHECK: 210000: 40 d0 3b d5 mrs x0, TPIDR_EL0 #CHECK: 210004: 00 00 40 91 add x0, x0, #0, lsl #12 #CHECK: 210008: 00 40 00 91 add x0, x0, #16 +#CHECK: 21000c: 40 d0 3b d5 mrs x0, TPIDR_EL0 +#CHECK: 210010: 00 fc 7f 91 add x0, x0, #4095, lsl #12 +#CHECK: 210014: 00 e0 3f 91 add x0, x0, #4088 -.type v1,@object .section .tbss,"awT",@nobits + +.type v1,@object .globl v1 .p2align 2 v1: .word 0 .size v1, 4 +# The current offset from the thread pointer is 20. Raise it to just below the +# 24-bit limit. +.space (0xfffff8 - 20) + +.type v2,@object +.globl v2 +.p2align 2 +v2: +.word 0 +.size v2, 4 |