[MCA] Don't assume that createMCInstrAnalysis() always returns a valid pointer.

Class InstrBuilder wrongly assumed that llvm targets were always able to return
a non-null pointer when createMCInstrAnalysis() was called on them.
This was causing crashes when simulating executions for targets that don't
provide an MCInstrAnalysis object.
This patch fixes the issue by making MCInstrAnalysis optional.

5 files changed, 91 insertions, 11 deletions

diff --git a/llvm/include/llvm/MCA/InstrBuilder.h b/llvm/include/llvm/MCA/InstrBuilder.h
index 0fadbce399b..5f998db5e4c 100644
--- a/llvm/include/llvm/MCA/InstrBuilder.h
+++ b/llvm/include/llvm/MCA/InstrBuilder.h
@@ -40,7 +40,7 @@ class InstrBuilder {
   const MCSubtargetInfo &STI;
   const MCInstrInfo &MCII;
   const MCRegisterInfo &MRI;
-  const MCInstrAnalysis &MCIA;
+  const MCInstrAnalysis *MCIA;
   SmallVector<uint64_t, 8> ProcResourceMasks;
 
   DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
@@ -61,7 +61,7 @@ class InstrBuilder {
 
 public:
   InstrBuilder(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
-               const MCRegisterInfo &RI, const MCInstrAnalysis &IA);
+               const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
 
   void clear() {
     VariantDescriptors.shrink_and_clear();
diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp
index 5e228a255f1..cd3b815c3a6 100644
--- a/llvm/lib/MCA/InstrBuilder.cpp
+++ b/llvm/lib/MCA/InstrBuilder.cpp
@@ -28,7 +28,7 @@ namespace mca {
 InstrBuilder::InstrBuilder(const llvm::MCSubtargetInfo &sti,
                            const llvm::MCInstrInfo &mcii,
                            const llvm::MCRegisterInfo &mri,
-                           const llvm::MCInstrAnalysis &mcia)
+                           const llvm::MCInstrAnalysis *mcia)
     : STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), FirstCallInst(true),
       FirstReturnInst(true) {
   computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
@@ -587,12 +587,16 @@ InstrBuilder::createInstruction(const MCInst &MCI) {
   // Check if this is a dependency breaking instruction.
   APInt Mask;
 
-  unsigned ProcID = STI.getSchedModel().getProcessorID();
-  bool IsZeroIdiom = MCIA.isZeroIdiom(MCI, Mask, ProcID);
-  bool IsDepBreaking =
-      IsZeroIdiom || MCIA.isDependencyBreaking(MCI, Mask, ProcID);
-  if (MCIA.isOptimizableRegisterMove(MCI, ProcID))
-    NewIS->setOptimizableMove();
+  bool IsZeroIdiom = false;
+  bool IsDepBreaking = false;
+  if (MCIA) {
+    unsigned ProcID = STI.getSchedModel().getProcessorID();
+    IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);
+    IsDepBreaking =
+        IsZeroIdiom || MCIA->isDependencyBreaking(MCI, Mask, ProcID);
+    if (MCIA->isOptimizableRegisterMove(MCI, ProcID))
+      NewIS->setOptimizableMove();
+  }
 
   // Initialize Reads first.
   for (const ReadDescriptor &RD : D.Reads) {
@@ -649,7 +653,8 @@ InstrBuilder::createInstruction(const MCInst &MCI) {
 
   // Now query the MCInstrAnalysis object to obtain information about which
   // register writes implicitly clear the upper portion of a super-register.
-  MCIA.clearsSuperRegisters(MRI, MCI, WriteMask);
+  if (MCIA)
+    MCIA->clearsSuperRegisters(MRI, MCI, WriteMask);
 
   // Initialize writes.
   unsigned WriteIndex = 0;
diff --git a/llvm/test/tools/llvm-mca/SystemZ/lit.local.cfg b/llvm/test/tools/llvm-mca/SystemZ/lit.local.cfg
new file mode 100644
index 00000000000..5c02dd3614a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/SystemZ/lit.local.cfg
@@ -0,0 +1,3 @@
+if not 'SystemZ' in config.root.targets:
+    config.unsupported = True
+
diff --git a/llvm/test/tools/llvm-mca/SystemZ/stm-lm.s b/llvm/test/tools/llvm-mca/SystemZ/stm-lm.s
new file mode 100644
index 00000000000..5118635fff9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/SystemZ/stm-lm.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=s390x-linux-gnu -mcpu=z14 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
+
+stmg	%r6, %r15, 48(%r15)
+lmg	%r6, %r15, 48(%r15)
+
+# CHECK:      Iterations:        100
+# CHECK-NEXT: Instructions:      200
+# CHECK-NEXT: Total Cycles:      1003
+# CHECK-NEXT: Total uOps:        600
+
+# CHECK:      Dispatch Width:    6
+# CHECK-NEXT: uOps Per Cycle:    0.60
+# CHECK-NEXT: IPC:               0.20
+# CHECK-NEXT: Block RThroughput: 3.5
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  3      1     1.50           *            stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT:  3      10    2.50    *                   lmg	%r6, %r15, 48(%r15)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0.0] - Z14_FXaUnit
+# CHECK-NEXT: [0.1] - Z14_FXaUnit
+# CHECK-NEXT: [1.0] - Z14_FXbUnit
+# CHECK-NEXT: [1.1] - Z14_FXbUnit
+# CHECK-NEXT: [2.0] - Z14_LSUnit
+# CHECK-NEXT: [2.1] - Z14_LSUnit
+# CHECK-NEXT: [3]   - Z14_MCD
+# CHECK-NEXT: [4.0] - Z14_VBUnit
+# CHECK-NEXT: [4.1] - Z14_VBUnit
+# CHECK-NEXT: [5.0] - Z14_VecFPdUnit
+# CHECK-NEXT: [5.1] - Z14_VecFPdUnit
+# CHECK-NEXT: [6.0] - Z14_VecUnit
+# CHECK-NEXT: [6.1] - Z14_VecUnit
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0.0]  [0.1]  [1.0]  [1.1]  [2.0]  [2.1]  [3]    [4.0]  [4.1]  [5.0]  [5.1]  [6.0]  [6.1]
+# CHECK-NEXT:  -      -     1.50   1.50   2.06   4.94    -      -      -      -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0.0]  [0.1]  [1.0]  [1.1]  [2.0]  [2.1]  [3]    [4.0]  [4.1]  [5.0]  [5.1]  [6.0]  [6.1]  Instructions:
+# CHECK-NEXT:  -      -     1.50   1.50   1.96   0.04    -      -      -      -      -      -      -     stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT:  -      -      -      -     0.10   4.90    -      -      -      -      -      -      -     lmg	%r6, %r15, 48(%r15)
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     0123456789          012
+# CHECK-NEXT: Index     0123456789          0123456789
+
+# CHECK:      [0,0]     DeER .    .    .    .    .    . .   stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [0,1]     DeeeeeeeeeeER  .    .    .    . .   lmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [1,0]     .D=========eER .    .    .    . .   stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [1,1]     .D=========eeeeeeeeeeER  .    . .   lmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [2,0]     . D==================eER .    . .   stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [2,1]     . D==================eeeeeeeeeeER   lmg	%r6, %r15, 48(%r15)
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     3     10.0   0.3    0.0       stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: 1.     3     10.0   0.3    0.0       lmg	%r6, %r15, 48(%r15)
diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp
index 310b0bfad93..d0da3b85c28 100644
--- a/llvm/tools/llvm-mca/llvm-mca.cpp
+++ b/llvm/tools/llvm-mca/llvm-mca.cpp
@@ -378,7 +378,7 @@ int main(int argc, char **argv) {
     Width = DispatchWidth;
 
   // Create an instruction builder.
-  mca::InstrBuilder IB(*STI, *MCII, *MRI, *MCIA);
+  mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
 
   // Create a context to control ownership of the pipeline hardware.
   mca::Context MCA(*MRI, *STI);