diff options
| author | Tim Shen <timshen91@gmail.com> | 2018-06-21 21:29:54 +0000 |
|---|---|---|
| committer | Tim Shen <timshen91@gmail.com> | 2018-06-21 21:29:54 +0000 |
| commit | 03bb69ae5813c1575e2d2d75963ab788993e14cb (patch) | |
| tree | 61b7c1ed4feec0301cab2c9c50b5eef528b9d465 /polly | |
| parent | 6c9ee4a4a438a8059aacc809b2dd57128fccd6b3 (diff) | |
[SCEV] Re-apply r335197 (with Polly fixes).
Summary:
This initiates a discussion on changing Polly accordingly while re-applying r335197 (D48338).
I have never worked on Polly. The proposed change to param_div_div_div_2.ll is not educated, but just patterns that match the output.
All LLVM files are already reviewed in D48338.
Reviewers: jdoerfert, bollu, efriedma
Subscribers: jlebar, sanjoy, hiraditya, llvm-commits, bixia
Differential Revision: https://reviews.llvm.org/D48453
Diffstat (limited to 'polly')
| -rw-r--r-- | polly/test/Isl/CodeGen/param_div_div_div_2.ll | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/polly/test/Isl/CodeGen/param_div_div_div_2.ll b/polly/test/Isl/CodeGen/param_div_div_div_2.ll index 117687b96f9..883c0bd5ec1 100644 --- a/polly/test/Isl/CodeGen/param_div_div_div_2.ll +++ b/polly/test/Isl/CodeGen/param_div_div_div_2.ll @@ -5,23 +5,27 @@ ; their domain. ; ; CHECK: Invalid Context: -; CHECK-NEXT: [p_0] -> { : p_0 < 0 } -; CHECK-NEXT: p0: ((%a /u %b) /u (%c /u %d)) +; CHECK-NEXT: [p_0] -> { : false } +; CHECK-NEXT: p0: (((zext i32 %a to i64) /u (zext i32 %b to i64)) /u ((zext i32 %c to i64) /u (zext i32 %d to i64))) ; ; void f(unsigned *A, unsigned a, unsigned b, unsigned c, unsigned d) { ; for (unsigned i; i < 100; i++) ; A[i] += A[(a / b) / (c / d)]; ; } ; -; IR: %[[R0:[.a-zA-Z0-9]*]] = icmp ugt i32 %b, 1 -; IR-NEXT: %[[R1:[.a-zA-Z0-9]*]] = select i1 %[[R0]], i32 %b, i32 1 -; IR-NEXT: %[[R2:[.a-zA-Z0-9]*]] = udiv i32 %a, %[[R1]] -; IR-NEXT: %[[R5:[.a-zA-Z0-9]*]] = icmp ugt i32 %d, 1 -; IR-NEXT: %[[R6:[.a-zA-Z0-9]*]] = select i1 %[[R5]], i32 %d, i32 1 -; IR-NEXT: %[[R7:[.a-zA-Z0-9]*]] = udiv i32 %c, %[[R6]] -; IR-NEXT: %[[R3:[.a-zA-Z0-9]*]] = icmp ugt i32 %[[R7]], 1 -; IR-NEXT: %[[R4:[.a-zA-Z0-9]*]] = select i1 %[[R3]], i32 %[[R7]], i32 1 -; IR-NEXT: %[[R8:[.a-zA-Z0-9]*]] = udiv i32 %[[R2]], %[[R4]] +; IR: %[[A:[.a-zA-Z0-9]*]] = zext i32 %a to i64 +; IR-NEXT: %[[B:[.a-zA-Z0-9]*]] = zext i32 %b to i64 +; IR-NEXT: %[[R0:[.a-zA-Z0-9]*]] = icmp ugt i64 %[[B]], 1 +; IR-NEXT: %[[R1:[.a-zA-Z0-9]*]] = select i1 %[[R0]], i64 %[[B]], i64 1 +; IR-NEXT: %[[R2:[.a-zA-Z0-9]*]] = udiv i64 %[[A]], %[[R1]] +; IR-NEXT: %[[C:[.a-zA-Z0-9]*]] = zext i32 %c to i64 +; IR-NEXT: %[[D:[.a-zA-Z0-9]*]] = zext i32 %d to i64 +; IR-NEXT: %[[R5:[.a-zA-Z0-9]*]] = icmp ugt i64 %[[D]], 1 +; IR-NEXT: %[[R6:[.a-zA-Z0-9]*]] = select i1 %[[R5]], i64 %[[D]], i64 1 +; IR-NEXT: %[[R7:[.a-zA-Z0-9]*]] = udiv i64 %[[C]], %[[R6]] +; IR-NEXT: %[[R3:[.a-zA-Z0-9]*]] = icmp ugt i64 %[[R7]], 1 +; IR-NEXT: %[[R4:[.a-zA-Z0-9]*]] = select i1 %[[R3]], i64 %[[R7]], i64 1 +; IR-NEXT: %[[R8:[.a-zA-Z0-9]*]] = udiv i64 %[[R2]], %[[R4]] ; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" |