diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 17 |
2 files changed, 9 insertions, 22 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 6c248bec441..17618d71305 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -240,17 +240,9 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { return TranslateLegalizeResults(Op, Result); case TargetLowering::Custom: if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) { - if (Lowered == Result) - return TranslateLegalizeResults(Op, Lowered); - Changed = true; - if (Lowered->getNumValues() != Op->getNumValues()) { - // This expanded to something other than the load. Assume the - // lowering code took care of any chain values, and just handle the - // returned value. - assert(Result.getValue(1).use_empty() && - "There are still live users of the old chain!"); - return LegalizeOp(Lowered); - } + assert(Lowered->getNumValues() == Op->getNumValues() && + "Unexpected number of results"); + Changed = Lowered != Result; return TranslateLegalizeResults(Op, Lowered); } LLVM_FALLTHROUGH; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 79f5f875201..45f87bbaada 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -19849,7 +19849,6 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, // Replace chain users with the new chain. assert(NewLd->getNumValues() == 2 && "Loads must carry a chain!"); - DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewLd.getValue(1)); SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT, DAG.getBitcast(MVT::v8i1, NewLd), @@ -19910,10 +19909,10 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, // Replace chain users with the new chain. assert(Load->getNumValues() == 2 && "Loads must carry a chain!"); - DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1)); // Finally, do a normal sign-extend to the desired register. - return DAG.getSExtOrTrunc(Load, dl, RegVT); + SDValue SExt = DAG.getSExtOrTrunc(Load, dl, RegVT); + return DAG.getMergeValues({SExt, Load.getValue(1)}, dl); } // All sizes must be a power of two. @@ -20009,8 +20008,7 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, // If we have SSE4.1, we can directly emit a VSEXT node. if (Subtarget.hasSSE41()) { SDValue Sext = getExtendInVec(X86ISD::VSEXT, dl, RegVT, SlicedVec, DAG); - DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF); - return Sext; + return DAG.getMergeValues({Sext, TF}, dl); } // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest @@ -20019,15 +20017,13 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!"); SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT); - DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF); - return Shuff; + return DAG.getMergeValues({Shuff, TF}, dl); } if (Ext == ISD::EXTLOAD && !Subtarget.hasBWI() && RegVT == MVT::v8i64 && MemVT == MVT::v8i8) { SDValue Sext = getExtendInVec(X86ISD::VZEXT, dl, RegVT, SlicedVec, DAG); - DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF); - return Sext; + return DAG.getMergeValues({Sext, TF}, dl); } // Redistribute the loaded elements into the different locations. @@ -20040,8 +20036,7 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, // Bitcast to the requested type. Shuff = DAG.getBitcast(RegVT, Shuff); - DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF); - return Shuff; + return DAG.getMergeValues({Shuff, TF}, dl); } /// Return true if node is an ISD::AND or ISD::OR of two X86ISD::SETCC nodes |