diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 38 |
1 files changed, 15 insertions, 23 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fd00185a11a..f0f5f6fc181 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -31624,6 +31624,14 @@ static SDValue combineX86ShufflesRecursively( AllowVariableMask, DAG, Subtarget); } +/// Helper entry wrapper to combineX86ShufflesRecursively. +static SDValue combineX86ShufflesRecursively(SDValue Op, SelectionDAG &DAG, + const X86Subtarget &Subtarget) { + return combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 1, + /*HasVarMask*/ false, + /*AllowVarMask*/ true, DAG, Subtarget); +} + /// Get the PSHUF-style mask from PSHUF node. /// /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4 @@ -32434,9 +32442,7 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG, // specific PSHUF instruction sequences into their minimal form so that we // can evaluate how many specialized shuffle instructions are involved in // a particular chain. - if (SDValue Res = combineX86ShufflesRecursively( - {Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; // Simplify source operands based on shuffle mask. @@ -35819,10 +35825,7 @@ static SDValue combineVectorPack(SDNode *N, SelectionDAG &DAG, // Attempt to combine as shuffle. SDValue Op(N, 0); - if (SDValue Res = - combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, - /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; return SDValue(); @@ -35898,9 +35901,7 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG, // We can decode 'whole byte' logical bit shifts as shuffles. if (LogicalShift && (ShiftVal % 8) == 0) { SDValue Op(N, 0); - if (SDValue Res = combineX86ShufflesRecursively( - {Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; } @@ -35941,10 +35942,7 @@ static SDValue combineVectorInsert(SDNode *N, SelectionDAG &DAG, // Attempt to combine PINSRB/PINSRW patterns to a shuffle. SDValue Op(N, 0); - if (SDValue Res = - combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, - /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; return SDValue(); @@ -36461,9 +36459,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG, // Attempt to recursively combine a bitmask AND with shuffles. if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) { SDValue Op(N, 0); - if (SDValue Res = combineX86ShufflesRecursively( - {Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; } @@ -36777,9 +36773,7 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG, // Attempt to recursively combine an OR of shuffles. if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) { SDValue Op(N, 0); - if (SDValue Res = combineX86ShufflesRecursively( - {Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; } @@ -39083,9 +39077,7 @@ static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG, // Attempt to recursively combine a bitmask ANDNP with shuffles. if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) { SDValue Op(N, 0); - if (SDValue Res = combineX86ShufflesRecursively( - {Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) + if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) return Res; } |