1 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 91034030f6e..6d4ee217cf1 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -348,19 +348,22 @@ void GCNScheduleDAGMILive::schedule() {
     if (MI->getIterator() != RegionEnd) {
       BB->remove(MI);
       BB->insert(RegionEnd, MI);
-      if (LIS) {
+      if (LIS)
         LIS->handleMove(*MI, true);
-        RegisterOperands RegOpers;
-        RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
-        if (ShouldTrackLaneMasks) {
-          // Adjust liveness and add missing dead+read-undef flags.
-          SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
-          RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
-        } else {
-          // Adjust for missing dead-def flags.
-          RegOpers.detectDeadDefs(*MI, *LIS);
-        }
-      }
+    }
+    // Reset read-undef flags and update them later.
+    for (auto &Op : MI->operands())
+      if (Op.isReg() && Op.isDef())
+        Op.setIsUndef(false);
+    RegisterOperands RegOpers;
+    RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
+    if (ShouldTrackLaneMasks) {
+      // Adjust liveness and add missing dead+read-undef flags.
+      SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
+      RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
+    } else {
+      // Adjust for missing dead-def flags.
+      RegOpers.detectDeadDefs(*MI, *LIS);
     }
     RegionEnd = MI->getIterator();
     ++RegionEnd;