summaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
AgeCommit message (Expand)Author
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-05-22AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen
2018-04-25[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)Alexander Timofeev
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-01[AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
2017-08-08[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko
2017-08-04[AMDGPU] Add support for Whole Wavefront ModeConnor Abbott
2017-08-04[AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQMConnor Abbott
2017-08-03AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when ...Changpeng Fang
2017-06-20[AMDGPU] Eliminate SGPR to VGPR copy when possibleStanislav Mekhanoshin
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth
2017-04-29AMDGPU: Fix copies from physical registers in SIFixSGPRCopiesMatt Arsenault
2017-04-24[AMDGPU] Merge M0 initializationsStanislav Mekhanoshin
2017-04-12AMDGPU : Fix common dominator of two incoming blocks terminates with uniform ...Wei Ding
2017-04-11AMDGPU: Fix folding reg_sequence into copy to phys regMatt Arsenault
2017-01-13[CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus
2016-12-06AMDGPU/SI: Don't move copies of immediates to the VALUTom Stellard
2016-11-29AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar br...Tom Stellard
2016-11-11AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard
2016-10-01Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini
2016-07-09Revert "AMDGPU: Remove unused control flow intrinsic"Matt Arsenault
2016-07-08AMDGPU: Remove unused control flow intrinsicMatt Arsenault
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault
2016-04-21AMDGPU: Fix debug name of pass to better matchMatt Arsenault
2016-01-07AMDGPU/SI: Fold operands with sub-registersNicolai Haehnle
2015-11-03AMDGPU: Initialize SIFixSGPRCopies so -print-after worksMatt Arsenault
2015-11-02AMDGPU: Stop assuming vreg for build_vectorMatt Arsenault
2015-11-02AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCEMatt Arsenault
2015-10-13AMDGPU: Refactor isVGPRToSGPRCopyMatt Arsenault
2015-10-07AMDGPU: Remove inferRegClassFromUses / inferRegClassFromDefsMatt Arsenault
2015-10-01AMDGPU: Remove dead codeMatt Arsenault
2015-09-25AMDGPU: Fix recomputing dominator tree unnecessarilyMatt Arsenault
2015-09-21AMDGPU: Move copy handling under switch like other instructionsMatt Arsenault
2015-09-10AMDGPU: Simplify debug printingMatt Arsenault
2015-06-13R600 -> AMDGPU renameTom Stellard
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 14:34:16 +0000