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AgeCommit message (Expand)Author
2018-10-04[X86][LegalizeVectorOps] Use MERGE_VALUES to return two results from LowerLoa...Craig Topper
2018-10-04[SimplifyCFG] Change recursive calls to llvm::SimplifyCFG to instead use an o...Craig Topper
2018-10-04[WebAssembly] Don't modify preds/succs iterators while erasing from themHeejin Ahn
2018-10-04AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesaKonstantin Zhuravlyov
2018-10-04[COFF] [X86] Don't use llvm_unreachable for unsupported relocation typesMartin Storsjo
2018-10-04[InstCombine] reduce code duplication in SimplifyDemandedVectorElts; NFCISanjay Patel
2018-10-04Give same-named members unique timestamps on Darwin in llvm-ar.James Y Knight
2018-10-04[globalisel][combine] Improve the truncate placement for the extending-loads ...Daniel Sanders
2018-10-04[x86] add test for SSE sqrtss register dep (PR22206)Sanjay Patel
2018-10-04AArch64: Fix XSeqPairs/WSeqPairs problemsMatthias Braun
2018-10-04[AMDGPU] Match signed dot4/8 pattern.Farhana Aleen
2018-10-04[llvm-mca][x86] Add PR36951 ReadAfterLd test caseSimon Pilgrim
2018-10-04[InstCombine] allow bitcast to/from FP for vector insert/extract transformSanjay Patel
2018-10-04[llvm-mca] Move field 'AllowZeroMoveEliminationOnly' to class RegisterFile. NFC.Andrea Di Biagio
2018-10-04[X86][AVX] Add PR39161 test case for v4f64 zzww shuffleSimon Pilgrim
2018-10-04[utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical...Greg Bedwell
2018-10-04[utils] simple refactor in update_mca_test_checks.py to make intent more read...Greg Bedwell
2018-10-04[RISCV] Remove overzealous is64Bit checksAlex Bradbury
2018-10-04[X86] Set correct MMO offset on scalarized load piecesDavid Greene
2018-10-04[llvm-mca][x86] Add tests demonstrating ReadAfterLd delaySimon Pilgrim
2018-10-04[PassTimingInfo] cleanup on TimingData's Timer handlingFedor Sergeev
2018-10-04[llvm-exegesis][NFC] Improve parsing of the YAML filesGuillaume Chatelet
2018-10-04[doc] Update the programmer's manual about SmallSet's iteratorKristof Umann
2018-10-04[llvm-mca] Check for inconsistencies when constructing instruction descriptors.Andrea Di Biagio
2018-10-04Fix MSVC "not all control paths return a value" warning. NFCI.Simon Pilgrim
2018-10-04[RISCV][NFC] Remove dead CHECK lines from vararg.ll testAlex Bradbury
2018-10-04[RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32FAlex Bradbury
2018-10-04[llvm-exegesis][NFC] Test sched class names only in !NDEBUG mode.Clement Courbet
2018-10-04[X86] Merge matchANDXORWithAllOnesAsANDNP into combineANDXORWithAllOnesIntoAN...Craig Topper
2018-10-04[RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}linaro-local/ci/tcwg-llvm-kernel-baseline-aarch64-master-stableAlex Bradbury
2018-10-04[llvm-exegesis] Unbreak analysis-uops-variant.test introduced in D52825Fangrui Song
2018-10-04[LegalizeIntegerTypes] Fix typo in comment. NFCCraig Topper
2018-10-03[WebAssembly] Add WebAssembly to LLVM_ALL_TARGETSDerek Schuff
2018-10-03[llvm-nm] Print an explicit "no symbols" message when an object file has no s...Jordan Rupprecht
2018-10-03[RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombineAlex Bradbury
2018-10-03[WebAssembly] Bitselect intrinsic and instructionThomas Lively
2018-10-03[RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLoweringAlex Bradbury
2018-10-03[WebAssembly] Refactor WasmSignature and use it for MCSymbolWasmDerek Schuff
2018-10-03[machineverifier] Detect PHI's that are preceeded by non-PHI'sDaniel Sanders
2018-10-03[mips] Remove -allow-deprecated-dag-overlap flag from tests. NFCSimon Atanasyan
2018-10-03[InstCombine] allow SimplifyDemandedVectorElts to work with FP binopsSanjay Patel
2018-10-03Make meanings of variables clearer in action table generation (NFC)Heejin Ahn
2018-10-03[X86] Stop promoting vector ISD::SELECT to vXi64.Craig Topper
2018-10-03[InstCombine] add tests for binop undef-into-constant propagation; NFCSanjay Patel
2018-10-03[X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned v2i1/v4i1...Craig Topper
2018-10-03[RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction...Alex Bradbury
2018-10-03[X86] Add CMOV pseudos for VR128X and VR256X register classes. Use them when ...Craig Topper
2018-10-03[X86] Don't break CMOV pseudo instructions down by type. Just by register class.Craig Topper
2018-10-03[X86] PUSH/POP 'mem-mem' instructions are not RMW - these are 2 different add...Simon Pilgrim
2018-10-03Emit template type and value parameter DIEs for template variables.Matthew Voss
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