From d9149ca7a4aad504a43ca825e51fc4bbb011cb59 Mon Sep 17 00:00:00 2001 From: "Ivan A. Kosarev" Date: Thu, 5 Jul 2018 08:59:49 +0000 Subject: [NEON] Fix combining of vldx_dup intrinsics with updating of base addresses Resolves: Unsupported ARM Neon intrinsics in Target-specific DAG combine function for VLDDUP https://bugs.llvm.org/show_bug.cgi?id=38031 Related diff: D48439 Differential Revision: https://reviews.llvm.org/D48920 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'llvm/lib/Target/ARM') diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 6e5942fb6ed..9b143dcff73 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -11488,6 +11488,12 @@ static SDValue CombineBaseUpdate(SDNode *N, NumVecs = 3; break; case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; NumVecs = 4; break; + case Intrinsic::arm_neon_vld2dup: + case Intrinsic::arm_neon_vld3dup: + case Intrinsic::arm_neon_vld4dup: + // TODO: Support updating VLDxDUP nodes. For now, we just skip + // combining base updates for such intrinsics. + continue; case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; NumVecs = 2; isLaneOp = true; break; case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; -- cgit v1.2.3