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//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone enum definitions for the RISCV target
// useful for the compiler back-end and the MC libraries.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/SubtargetFeature.h"
namespace llvm {
// RISCVII - This namespace holds all of the target specific flags that
// instruction info tracks. All definitions must match RISCVInstrFormats.td.
namespace RISCVII {
enum {
InstFormatPseudo = 0,
InstFormatR = 1,
InstFormatR4 = 2,
InstFormatI = 3,
InstFormatS = 4,
InstFormatB = 5,
InstFormatU = 6,
InstFormatJ = 7,
InstFormatCR = 8,
InstFormatCI = 9,
InstFormatCSS = 10,
InstFormatCIW = 11,
InstFormatCL = 12,
InstFormatCS = 13,
InstFormatCB = 14,
InstFormatCJ = 15,
InstFormatOther = 16,
InstFormatMask = 31
};
enum {
MO_None,
MO_LO,
MO_HI,
MO_PCREL_HI,
};
} // namespace RISCVII
// Describes the predecessor/successor bits used in the FENCE instruction.
namespace RISCVFenceField {
enum FenceField {
I = 8,
O = 4,
R = 2,
W = 1
};
}
// Describes the supported floating point rounding mode encodings.
namespace RISCVFPRndMode {
enum RoundingMode {
RNE = 0,
RTZ = 1,
RDN = 2,
RUP = 3,
RMM = 4,
DYN = 7,
Invalid
};
inline static StringRef roundingModeToString(RoundingMode RndMode) {
switch (RndMode) {
default:
llvm_unreachable("Unknown floating point rounding mode");
case RISCVFPRndMode::RNE:
return "rne";
case RISCVFPRndMode::RTZ:
return "rtz";
case RISCVFPRndMode::RDN:
return "rdn";
case RISCVFPRndMode::RUP:
return "rup";
case RISCVFPRndMode::RMM:
return "rmm";
case RISCVFPRndMode::DYN:
return "dyn";
}
}
inline static RoundingMode stringToRoundingMode(StringRef Str) {
return StringSwitch<RoundingMode>(Str)
.Case("rne", RISCVFPRndMode::RNE)
.Case("rtz", RISCVFPRndMode::RTZ)
.Case("rdn", RISCVFPRndMode::RDN)
.Case("rup", RISCVFPRndMode::RUP)
.Case("rmm", RISCVFPRndMode::RMM)
.Case("dyn", RISCVFPRndMode::DYN)
.Default(RISCVFPRndMode::Invalid);
}
inline static bool isValidRoundingMode(unsigned Mode) {
switch (Mode) {
default:
return false;
case RISCVFPRndMode::RNE:
case RISCVFPRndMode::RTZ:
case RISCVFPRndMode::RDN:
case RISCVFPRndMode::RUP:
case RISCVFPRndMode::RMM:
case RISCVFPRndMode::DYN:
return true;
}
}
} // namespace RISCVFPRndMode
namespace RISCVSysReg {
struct SysReg {
const char *Name;
unsigned Encoding;
// FIXME: add these additional fields when needed.
// Privilege Access: Read, Write, Read-Only.
// unsigned ReadWrite;
// Privilege Mode: User, System or Machine.
// unsigned Mode;
// Check field name.
// unsigned Extra;
// Register number without the privilege bits.
// unsigned Number;
FeatureBitset FeaturesRequired;
bool isRV32Only;
bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
// Not in 32-bit mode.
if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
return false;
// No required feature associated with the system register.
if (FeaturesRequired.none())
return true;
return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
}
};
#define GET_SysRegsList_DECL
#include "RISCVGenSystemOperands.inc"
} // end namespace RISCVSysReg
} // namespace llvm
#endif
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