aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSlava Gurevich <sgurevich@gmail.com>2022-08-05 18:15:45 -0700
committerSlava Gurevich <sgurevich@gmail.com>2022-08-05 18:33:18 -0700
commitbcac7b3acb1972bdfabe3c84f51243e9a353e7fe (patch)
tree7ea5ecabe0f2a3fbec9c99367641150ef687b2e6
parentd7cbfcf36ace575ec90434624279dd3ebce78c47 (diff)
[LLDB] Missing break in a switch statement alters the execution flow.linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O3
Looks like a typo from the past code changes. Differential Revision: https://reviews.llvm.org/D131244
-rw-r--r--lldb/source/Plugins/Process/Utility/ARMUtils.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/lldb/source/Plugins/Process/Utility/ARMUtils.h b/lldb/source/Plugins/Process/Utility/ARMUtils.h
index bbe4c9a35fa6..a7aaa5ac7a1f 100644
--- a/lldb/source/Plugins/Process/Utility/ARMUtils.h
+++ b/lldb/source/Plugins/Process/Utility/ARMUtils.h
@@ -25,7 +25,8 @@ static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5,
ARM_ShifterType &shift_t) {
switch (type) {
default:
- // assert(0 && "Invalid shift type");
+ assert(0 && "Invalid shift type");
+ break;
case 0:
shift_t = SRType_LSL;
return imm5;
@@ -302,7 +303,7 @@ static inline uint32_t ARMExpandImm(uint32_t opcode) {
// (imm32, carry_out) = ThumbExpandImm_C(imm12, carry_in)
static inline uint32_t ThumbExpandImm_C(uint32_t opcode, uint32_t carry_in,
uint32_t &carry_out) {
- uint32_t imm32; // the expanded result
+ uint32_t imm32 = 0; // the expanded result
const uint32_t i = bit(opcode, 26);
const uint32_t imm3 = bits(opcode, 14, 12);
const uint32_t abcdefgh = bits(opcode, 7, 0);
@@ -311,6 +312,8 @@ static inline uint32_t ThumbExpandImm_C(uint32_t opcode, uint32_t carry_in,
if (bits(imm12, 11, 10) == 0) {
switch (bits(imm12, 9, 8)) {
default: // Keep static analyzer happy with a default case
+ break;
+
case 0:
imm32 = abcdefgh;
break;