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author | sstwcw <f0gukp2nk@protonmail.com> | 2022-07-28 23:39:46 +0000 |
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committer | sstwcw <f0gukp2nk@protonmail.com> | 2022-07-29 00:38:30 +0000 |
commit | 6db0c18b1af653f33dd4629d6155f6cf334a975e (patch) | |
tree | 2271d021a82ea484e0ac8dbb40eea0d235cb2cfb /clang/unittests | |
parent | 67480b360ca0dcc33fe3126d0602b3d358dfbc6f (diff) |
[clang-format] Handle Verilog modules
Now things inside hierarchies like modules and interfaces are
indented. When the module header spans multiple lines, all except the
first line are indented as continuations. We added the property
`IsContinuation` to mark lines that should be indented this way.
In order that the colons inside square brackets don't get labeled as
`TT_ObjCMethodExpr`, we added a check to only use this type when the
language is not Verilog.
Differential Revision: https://reviews.llvm.org/D128712
Diffstat (limited to 'clang/unittests')
-rw-r--r-- | clang/unittests/Format/FormatTestVerilog.cpp | 69 | ||||
-rw-r--r-- | clang/unittests/Format/TokenAnnotatorTest.cpp | 7 |
2 files changed, 76 insertions, 0 deletions
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp index 30fe334a83f5..8b3b10c982ef 100644 --- a/clang/unittests/Format/FormatTestVerilog.cpp +++ b/clang/unittests/Format/FormatTestVerilog.cpp @@ -139,6 +139,75 @@ TEST_F(FormatTestVerilog, Delay) { "x = x;")); } +TEST_F(FormatTestVerilog, Hierarchy) { + verifyFormat("module x;\n" + "endmodule"); + // Test that the end label is on the same line as the end keyword. + verifyFormat("module x;\n" + "endmodule : x"); + // Test that things inside are indented. + verifyFormat("module x;\n" + " generate\n" + " endgenerate\n" + "endmodule"); + verifyFormat("program x;\n" + " generate\n" + " endgenerate\n" + "endprogram"); + verifyFormat("interface x;\n" + " generate\n" + " endgenerate\n" + "endinterface"); + verifyFormat("task x;\n" + " generate\n" + " endgenerate\n" + "endtask"); + verifyFormat("function x;\n" + " generate\n" + " endgenerate\n" + "endfunction"); + verifyFormat("class x;\n" + " generate\n" + " endgenerate\n" + "endclass"); + // Test that they nest. + verifyFormat("module x;\n" + " program x;\n" + " program x;\n" + " endprogram\n" + " endprogram\n" + "endmodule"); + // Test that an extern declaration doesn't change the indentation. + verifyFormat("extern module x;\n" + "x = x;"); + // Test complex headers + verifyFormat("extern module x\n" + " import x.x::x::*;\n" + " import x;\n" + " #(parameter x)\n" + " (output x);"); + verifyFormat("module x\n" + " import x.x::x::*;\n" + " import x;\n" + " #(parameter x)\n" + " (output x);\n" + " generate\n" + " endgenerate\n" + "endmodule : x"); + verifyFormat("virtual class x\n" + " (x)\n" + " extends x(x)\n" + " implements x, x, x;\n" + " generate\n" + " endgenerate\n" + "endclass : x\n"); + verifyFormat("function automatic logic [1 : 0] x\n" + " (input x);\n" + " generate\n" + " endgenerate\n" + "endfunction : x"); +} + TEST_F(FormatTestVerilog, If) { verifyFormat("if (x)\n" " x = x;"); diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index afc673961caf..9fe89eead213 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -831,6 +831,13 @@ TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) { ASSERT_EQ(Tokens.size(), 7u); EXPECT_TOKEN(Tokens[1], tok::colon, TT_VerilogBlockLabelColon); EXPECT_TOKEN(Tokens[4], tok::colon, TT_VerilogBlockLabelColon); + // Test that the dimension colon is annotated correctly. + Tokens = Annotate("var [1 : 0] x;"); + ASSERT_EQ(Tokens.size(), 9u) << Tokens; + EXPECT_TOKEN(Tokens[3], tok::colon, TT_BitFieldColon); + Tokens = Annotate("extern function [1 : 0] x;"); + ASSERT_EQ(Tokens.size(), 10u) << Tokens; + EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon); } } // namespace |