ci/qemu.git - [no description]

Age	Commit message (Expand)	Author
2022-05-24	hw/riscv/sifive_u: Resolve redundant property accessors	Bernhard Beschow
2022-05-24	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	Tsukasa OI
2022-04-29	hw/riscv: Don't add empty bootargs to device tree	Bin Meng
2022-01-08	hw/riscv: Use error_fatal for SoC realisation	Alistair Francis
2021-12-15	hw: Replace trivial drive_get_next() by drive_get()	Markus Armbruster
2021-12-15	hw/sd/ssi-sd: Do not create SD card within controller's realize	Markus Armbruster
2021-10-28	hw/riscv: sifive_u: Use the PLIC config helper function	Alistair Francis
2021-10-22	hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id	Bin Meng
2021-09-21	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	Anup Patel
2021-09-21	hw/intc: Rename sifive_clint sources to riscv_aclint sources	Anup Patel
2021-09-21	sifive_u: Connect the SiFive PWM device	Alistair Francis
2021-09-21	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis
2021-08-26	arch_init.h: Don't include arch_init.h unnecessarily	Peter Maydell
2021-07-15	hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned	Bin Meng
2021-07-15	hw/riscv: sifive_u: Correct the CLINT timebase frequency	Bin Meng
2021-06-08	hw/riscv: Use macros for BIOS image names	Bin Meng
2021-06-08	hw/riscv: Support the official PLIC DT bindings	Bin Meng
2021-06-08	hw/riscv: Support the official CLINT DT bindings	Bin Meng
2021-06-08	hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper	Bin Meng
2021-05-02	hw: Do not include qemu/log.h if it is not necessary	Thomas Huth
2021-03-04	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng
2021-03-04	hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card	Bin Meng
2021-03-04	hw/riscv: sifive_u: Add QSPI0 controller and connect a flash	Bin Meng
2021-01-16	riscv: Pass RISCVHartArrayState by pointer	Alistair Francis
2021-01-16	hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type	Bin Meng
2020-12-17	hw/riscv: Use the CPU to determine if 32-bit	Alistair Francis
2020-12-17	hw/riscv: sifive_u: Remove compile time XLEN checks	Alistair Francis
2020-12-17	hw/riscv: boot: Remove compile time XLEN checks	Alistair Francis
2020-12-17	hw/riscv: sifive_u: Add UART1 DT node in the generated DTB	Anup Patel
2020-12-15	vl: make qemu_get_machine_opts static	Paolo Bonzini
2020-11-03	hw/riscv: sifive_u: Allow passing custom DTB	Anup Patel
2020-10-22	hw/riscv: Load the kernel after the firmware	Alistair Francis
2020-10-22	hw/riscv: sifive_u: Allow specifying the CPU	Alistair Francis
2020-09-22	sifive_u: Register "start-in-flash" as class property	Eduardo Habkost
2020-09-18	sifive_u: Rename memmap enum constants	Eduardo Habkost
2020-09-09	hw/riscv: Move sifive_uart model to hw/char	Bin Meng
2020-09-09	hw/riscv: Move sifive_plic model to hw/intc	Bin Meng
2020-09-09	hw/riscv: Move sifive_clint model to hw/intc	Bin Meng
2020-09-09	hw/riscv: sifive_u: Connect a DMA controller	Bin Meng
2020-09-09	hw/riscv: clint: Avoid using hard-coded timebase frequency	Bin Meng
2020-09-09	target/riscv: cpu: Set reset vector based on the configured property value	Bin Meng
2020-08-25	hw/riscv: Allow creating multiple instances of PLIC	Anup Patel
2020-08-25	hw/riscv: Allow creating multiple instances of CLINT	Anup Patel
2020-08-21	hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u	Bin Meng
2020-08-21	hw/riscv: sifive_u: Add a dummy L2 cache controller device	Bin Meng
2020-07-21	hw: Mark nd_table[] misuse in realize methods FIXME	Markus Armbruster
2020-07-13	hw/riscv: Modify MROM size to end at 0x10000	Bin Meng
2020-07-13	RISC-V: Support 64 bit start address	Atish Patra
2020-07-13	riscv: Add opensbi firmware dynamic support	Atish Patra
2020-07-13	RISC-V: Copy the fdt in dram instead of ROM	Atish Patra