ci/qemu.git - [no description]

Age	Commit message (Expand)	Author
2022-06-10	hw/riscv: virt: Generate fw_cfg DT node correctly	Atish Patra
2022-05-24	hw/riscv: virt: Fix interrupt parent for dynamic platform devices	Anup Patel
2022-05-24	hw/riscv: Make CPU config error handling generous (virt/spike)	Tsukasa OI
2022-04-29	hw/riscv: Enable TPM backends	Alistair Francis
2022-04-29	hw/riscv: virt: Add device plug support	Alistair Francis
2022-04-29	hw/riscv: virt: Add support for generating platform FDT entries	Alistair Francis
2022-04-29	hw/riscv: virt: Create a platform bus	Alistair Francis
2022-04-29	hw/riscv: virt: Add a machine done notifier	Alistair Francis
2022-04-29	hw/riscv: Don't add empty bootargs to device tree	Bin Meng
2022-04-22	hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled	Niklas Cassel
2022-04-22	hw/riscv: virt: Exit if the user provided -bios in combination with KVM	Ralf Ramsauer
2022-03-03	hw/riscv: virt: Increase maximum number of allowed CPUs	Anup Patel
2022-03-03	hw/riscv: virt: Add optional AIA IMSIC support to virt machine	Anup Patel
2022-03-03	hw/riscv: virt: Add optional AIA APLIC support to virt machine	Anup Patel
2022-02-16	hw/riscv: virt: Use AIA INTC compatible string when available	Anup Patel
2022-01-21	target/riscv: Support start kernel directly by KVM	Yifei Jiang
2021-10-28	hw/riscv: virt: Use the PLIC config helper function	Alistair Francis
2021-10-28	hw/riscv: virt: Don't use a macro for the PLIC configuration	Alistair Francis
2021-10-22	hw/riscv: virt: Use machine->ram as the system memory	Mingwang Li
2021-09-21	hw/riscv: virt: Add optional ACLINT support to virt machine	Anup Patel
2021-09-21	hw/riscv: virt: Re-factor FDT generation	Anup Patel
2021-09-21	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	Anup Patel
2021-09-21	hw/intc: Rename sifive_clint sources to riscv_aclint sources	Anup Patel
2021-09-21	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis
2021-09-01	hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()	Peter Maydell
2021-09-01	hw/riscv: virt: Move flash node to root	Bin Meng
2021-08-26	arch_init.h: Don't include arch_init.h unnecessarily	Peter Maydell
2021-06-08	hw/riscv: Use macros for BIOS image names	Bin Meng
2021-06-08	hw/riscv: Support the official PLIC DT bindings	Bin Meng
2021-06-08	hw/riscv: Support the official CLINT DT bindings	Bin Meng
2021-06-08	hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper	Bin Meng
2021-05-02	hw: Do not include qemu/log.h if it is not necessary	Thomas Huth
2021-03-22	hw/riscv: allow ramfb on virt	Asherah Connor
2021-03-22	hw/riscv: Add fw_cfg support to virt	Asherah Connor
2021-03-10	hw/riscv: migrate fdt field to generic MachineState	Alex Bennée
2021-03-04	hw/riscv: virt: Map high mmio for PCIe	Bin Meng
2021-03-04	hw/riscv: virt: Limit RAM size in a 32-bit system	Bin Meng
2021-03-04	hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()	Bin Meng
2021-03-04	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng
2021-01-16	riscv: Pass RISCVHartArrayState by pointer	Alistair Francis
2020-12-17	hw/riscv: Use the CPU to determine if 32-bit	Alistair Francis
2020-12-17	hw/riscv: virt: Remove compile time XLEN checks	Alistair Francis
2020-12-17	hw/riscv: boot: Remove compile time XLEN checks	Alistair Francis
2020-12-17	riscv: virt: Remove target macro conditionals	Alistair Francis
2020-12-15	vl: make qemu_get_machine_opts static	Paolo Bonzini
2020-11-03	hw/riscv: virt: Allow passing custom DTB	Anup Patel
2020-10-22	hw/riscv: Load the kernel after the firmware	Alistair Francis
2020-09-09	hw/riscv: Move sifive_test model to hw/misc	Bin Meng
2020-09-09	hw/riscv: Move sifive_plic model to hw/intc	Bin Meng
2020-09-09	hw/riscv: Move sifive_clint model to hw/intc	Bin Meng