Revert bzr115014 as it causes an ICE when reloading sp = rx + n.

4 files changed, 28 insertions, 22 deletions

diff --git a/ChangeLog.linaro b/ChangeLog.linaro
index 42dff4b4c84..e0bfacf688d 100644
--- a/ChangeLog.linaro
+++ b/ChangeLog.linaro
@@ -1,3 +1,24 @@
+2012-09-07  Michael Hope  <michael.hope@linaro.org>
+
+	LP: #1046999
+	Revert:
+
+	gcc/
+	2012-08-17  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.md (arm_addsi3): New variant for Thumb2 16-bit ADD instruction.
+	* arm.c (thumb2_reorg): Don't convert an ADD instruction that's
+	already 16 bits.
+
+	Backport from mainline r190530:
+
+	gcc/testsuite/
+	2012-08-20  Richard Earnshaw  <rearnsha@arm.com>
+
+	* gcc.target/arm/thumb-16bit-ops.c (f): This test uses a 16-bit
+	add instruction.
+	(f2): New test that really does need adds.
+
 2012-09-05  Christophe Lyon  <christophe.lyon@linaro.org>
 
 	Backport from mainline r190911:
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4c38c012a5a..25f4430d68a 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -13416,13 +13416,6 @@ thumb2_reorg (void)
 		  switch (GET_CODE (src))
 		    {
 		    case PLUS:
-		      /* Adding two registers and storing the result
-			 in the first source is already a 16-bit
-			 operation.  */
-		      if (rtx_equal_p (dst, op0)
-			  && register_operand (op1, SImode))
-			break;
-
 		      if (low_register_operand (op0, SImode))
 			{
 			  /* ADDS <Rd>,<Rn>,<Rm>  */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 47e4dec67da..320f04af505 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -726,12 +726,11 @@
 ;;  (plus (reg rN) (reg sp)) into (reg rN).  In this case reload will
 ;; put the duplicated register first, and not try the commutative version.
 (define_insn_and_split "*arm_addsi3"
-  [(set (match_operand:SI          0 "s_register_operand" "=rk,r ,k, r,r, k, r, k,r, k, r")
-	(plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, rk,k,rk,k, rk")
-		 (match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]
+  [(set (match_operand:SI          0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r")
+	(plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk")
+		 (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]
   "TARGET_32BIT"
   "@
-   add%?\\t%0, %0, %2
    add%?\\t%0, %1, %2
    add%?\\t%0, %1, %2
    add%?\\t%0, %2, %1
@@ -753,9 +752,9 @@
 		      operands[1], 0);
   DONE;
   "
-  [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,16")
+  [(set_attr "length" "4,4,4,4,4,4,4,4,4,16")
    (set_attr "predicable" "yes")
-   (set_attr "arch" "t2,*,*,*,t2,t2,*,*,t2,t2,*")]
+   (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")]
 )
 
 (define_insn_and_split "*thumb1_addsi3"
diff --git a/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c b/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c
index 90407eb6872..bd4f4897f35 100644
--- a/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c
+++ b/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c
@@ -4,21 +4,14 @@
 /* { dg-options "-Os -fno-builtin -mthumb" } */
 
 int
-f (int a, int b)
+f (int a, int b )
 {
   return a + b;
 }
 
-/* { dg-final { scan-assembler "add	r0, r0, r1" } } */
+/* { dg-final { scan-assembler "adds	r0, r0, r1" } } */
 
 int
-f2 (int a, int b, int c)
-{
-  return b + c;
-}
-
-/* { dg-final { scan-assembler "adds	r0, r1, r2" } } */
-int
 g1 (int a)
 {
   return a + 255;