diff options
author | Charles Baylis <charles.baylis@linaro.org> | 2014-12-03 12:57:03 +0000 |
---|---|---|
committer | Charles Baylis <charles.baylis@linaro.org> | 2015-06-25 17:45:11 +0100 |
commit | 27b195cd9b281308e397a2a13ddb33f2a521774f (patch) | |
tree | 30bc1c0cbc3e024c5f921a36007c140e0448da04 | |
parent | 3cc70dc3acdf9e2672464c53f6c75bb84bdedb9c (diff) |
[AArch64] PR63870 Improve error messages for NEON single lane memory alinaro-local/cbaylis-test-2015-0625-1
ccess intrinsics
gcc/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
PR target/63870
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
Add qualifier_struct_load_store_lane_index.
(aarch64_types_loadstruct_lane_qualifiers): Use
qualifier_struct_load_store_lane_index for lane index argument for
last argument.
(aarch64_types_storestruct_lane_qualifiers): Ditto.
(builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_args): Add new argument describing mode of
builtin. Check lane bounds for arguments with
SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_builtin): Emit error for incorrect lane indices
if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_builtin): Handle arguments with
qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
aarch64_simd_expand_args.
* config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
vst[234]_lane with BUILTIN_VALLDIF.
* config/aarch64/aarch64-simd.md:
(aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
endianness reversal on lane index.
(aarch64_vec_load_lanesci_lane<mode>): Ditto.
(aarch64_vec_load_lanesxi_lane<mode>): Ditto.
(vec_store_lanesoi_lane<mode>): Use VALLDIF iterator. Fix typo
in attribute.
(vec_store_lanesci_lane<mode>): Use VALLDIF iterator.
(vec_store_lanesxi_lane<mode>): Ditto.
(aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
reversal of lane index.
(aarch64_ld3_lane<mode>): Ditto.
(aarch64_ld4_lane<mode>): Ditto.
(aarch64_st2_lane<mode>): Ditto.
(aarch64_st3_lane<mode>): Ditto.
(aarch64_st4_lane<mode>): Ditto.
* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
to qmode. Add new mode parameter. Update uses.
(__LD3_LANE_FUNC): Ditto.
(__LD4_LANE_FUNC): Ditto.
(__ST2_LANE_FUNC): Ditto.
(__ST3_LANE_FUNC): Ditto.
(__ST4_LANE_FUNC): Ditto.
gcc/testsuite/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
gcc/testsuite/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New test.
Change-Id: I9daef27b4e2198bf1555bf457fc63934fcaed079
136 files changed, 2291 insertions, 177 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index ec60955c6af..e3632ff68bf 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -119,7 +119,9 @@ enum aarch64_type_qualifiers /* Polynomial types. */ qualifier_poly = 0x100, /* Lane indices - must be in range, and flipped for bigendian. */ - qualifier_lane_index = 0x200 + qualifier_lane_index = 0x200, + /* Lane indices for single lane structure loads and stores. */ + qualifier_struct_load_store_lane_index = 0x400 }; typedef struct @@ -221,7 +223,7 @@ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum aarch64_type_qualifiers aarch64_types_loadstruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_const_pointer_map_mode, - qualifier_none, qualifier_none }; + qualifier_none, qualifier_struct_load_store_lane_index }; #define TYPES_LOADSTRUCT_LANE (aarch64_types_loadstruct_lane_qualifiers) static enum aarch64_type_qualifiers @@ -253,7 +255,7 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum aarch64_type_qualifiers aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, - qualifier_none, qualifier_none }; + qualifier_none, qualifier_struct_load_store_lane_index }; #define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers) #define CF0(N, X) CODE_FOR_aarch64_##N##X @@ -869,12 +871,14 @@ typedef enum SIMD_ARG_COPY_TO_REG, SIMD_ARG_CONSTANT, SIMD_ARG_LANE_INDEX, + SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX, SIMD_ARG_STOP } builtin_simd_arg; static rtx aarch64_simd_expand_args (rtx target, int icode, int have_retval, - tree exp, builtin_simd_arg *args) + tree exp, builtin_simd_arg *args, + enum machine_mode builtin_mode) { rtx pat; rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand. */ @@ -913,6 +917,19 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, op[opc] = copy_to_mode_reg (mode, op[opc]); break; + case SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX: + gcc_assert (opc > 1); + if (CONST_INT_P (op[opc])) + { + aarch64_simd_lane_bounds (op[opc], 0, + GET_MODE_NUNITS (builtin_mode), + exp); + /* Keep to GCC-vector-extension lane indices in the RTL. */ + op[opc] = + GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc]))); + } + goto constant_arg; + case SIMD_ARG_LANE_INDEX: /* Must be a previous operand into which this is an index. */ gcc_assert (opc > 0); @@ -927,6 +944,7 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, /* Fall through - if the lane index isn't a constant then the next case will error. */ case SIMD_ARG_CONSTANT: +constant_arg: if (!(*insn_data[icode].operand[opc].predicate) (op[opc], mode)) { @@ -1035,6 +1053,8 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) if (d->qualifiers[qualifiers_k] & qualifier_lane_index) args[k] = SIMD_ARG_LANE_INDEX; + else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index) + args[k] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX; else if (d->qualifiers[qualifiers_k] & qualifier_immediate) args[k] = SIMD_ARG_CONSTANT; else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate) @@ -1058,7 +1078,7 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) /* The interface to aarch64_simd_expand_args expects a 0 if the function is void, and a 1 if it is not. */ return aarch64_simd_expand_args - (target, icode, !is_void, exp, &args[1]); + (target, icode, !is_void, exp, &args[1], d->mode); } rtx diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index dd2bc47ae1e..d0f298a1f07 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -88,9 +88,9 @@ BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0) BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0) /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */ - BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0) - BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0) - BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0) + BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0) + BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0) + BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0) /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ BUILTIN_VDC (STORESTRUCT, st2, 0) BUILTIN_VDC (STORESTRUCT, st3, 0) @@ -100,9 +100,9 @@ BUILTIN_VQ (STORESTRUCT, st3, 0) BUILTIN_VQ (STORESTRUCT, st4, 0) - BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0) - BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0) - BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0) + BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0) + BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0) + BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0) BUILTIN_VQW (BINOP, saddl2, 0) BUILTIN_VQW (BINOP, uaddl2, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b90f93841f8..7346e74b91e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3919,10 +3919,13 @@ (unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD2_LANE))] "TARGET_SIMD" - "ld2\\t{%S0.<Vetype> - %T0.<Vetype>}[%3], %1" + { + operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3]))); + return "ld2\\t{%S0.<Vetype> - %T0.<Vetype>}[%3], %1"; + } [(set_attr "type" "neon_load2_one_lane")] ) @@ -3959,7 +3962,7 @@ (define_insn "vec_store_lanesoi_lane<mode>" [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST2_LANE))] "TARGET_SIMD" @@ -3967,7 +3970,7 @@ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); return "st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0"; } - [(set_attr "type" "neon_store3_one_lane<q>")] + [(set_attr "type" "neon_store2_one_lane<q>")] ) (define_expand "vec_store_lanesoi<mode>" @@ -4014,10 +4017,13 @@ (unspec:CI [(match_operand:<V_THREE_ELEM> 1 "aarch64_simd_struct_operand" "Utv") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_LD3_LANE))] "TARGET_SIMD" - "ld3\\t{%S0.<Vetype> - %U0.<Vetype>}[%3], %1" +{ + operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3]))); + return "ld3\\t{%S0.<Vetype> - %U0.<Vetype>}[%3], %1"; +} [(set_attr "type" "neon_load3_one_lane")] ) @@ -4054,7 +4060,7 @@ (define_insn "vec_store_lanesci_lane<mode>" [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST3_LANE))] "TARGET_SIMD" @@ -4109,10 +4115,13 @@ (unspec:XI [(match_operand:<V_FOUR_ELEM> 1 "aarch64_simd_struct_operand" "Utv") (match_operand:XI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_LD4_LANE))] "TARGET_SIMD" - "ld4\\t{%S0.<Vetype> - %V0.<Vetype>}[%3], %1" +{ + operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3]))); + return "ld4\\t{%S0.<Vetype> - %V0.<Vetype>}[%3], %1"; +} [(set_attr "type" "neon_load4_one_lane")] ) @@ -4149,7 +4158,7 @@ (define_insn "vec_store_lanesxi_lane<mode>" [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST4_LANE))] "TARGET_SIMD" @@ -4566,14 +4575,12 @@ (match_operand:DI 1 "register_operand" "w") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { machine_mode mode = <V_TWO_ELEM>mode; rtx mem = gen_rtx_MEM (mode, operands[1]); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode), - NULL); emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0], mem, operands[2], @@ -4586,14 +4593,12 @@ (match_operand:DI 1 "register_operand" "w") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { machine_mode mode = <V_THREE_ELEM>mode; rtx mem = gen_rtx_MEM (mode, operands[1]); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode), - NULL); emit_insn (gen_aarch64_vec_load_lanesci_lane<mode> (operands[0], mem, operands[2], @@ -4606,14 +4611,12 @@ (match_operand:DI 1 "register_operand" "w") (match_operand:XI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { machine_mode mode = <V_FOUR_ELEM>mode; rtx mem = gen_rtx_MEM (mode, operands[1]); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode), - NULL); emit_insn (gen_aarch64_vec_load_lanesxi_lane<mode> (operands[0], mem, operands[2], @@ -4850,54 +4853,45 @@ DONE; }) -(define_expand "aarch64_st2_lane<VQ:mode>" +(define_expand "aarch64_st2_lane<mode>" [(match_operand:DI 0 "register_operand" "r") (match_operand:OI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { machine_mode mode = <V_TWO_ELEM>mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem, - operands[1], - operands[2])); + emit_insn (gen_vec_store_lanesoi_lane<mode> (mem, operands[1], operands[2])); DONE; }) -(define_expand "aarch64_st3_lane<VQ:mode>" +(define_expand "aarch64_st3_lane<mode>" [(match_operand:DI 0 "register_operand" "r") (match_operand:CI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { machine_mode mode = <V_THREE_ELEM>mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem, - operands[1], - operands[2])); + emit_insn (gen_vec_store_lanesci_lane<mode> (mem, operands[1], operands[2])); DONE; }) -(define_expand "aarch64_st4_lane<VQ:mode>" +(define_expand "aarch64_st4_lane<mode>" [(match_operand:DI 0 "register_operand" "r") (match_operand:XI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { machine_mode mode = <V_FOUR_ELEM>mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem, - operands[1], - operands[2])); + emit_insn (gen_vec_store_lanesxi_lane<mode> (mem, operands[1], operands[2])); DONE; }) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 114994e48b7..fce557779c2 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -9950,8 +9950,8 @@ __STRUCTN (float, 64, 4) #undef __STRUCTN -#define __ST2_LANE_FUNC(intype, largetype, ptrtype, \ - mode, ptr_mode, funcsuffix, signedtype) \ +#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode, \ + qmode, ptr_mode, funcsuffix, signedtype) \ __extension__ static __inline void \ __attribute__ ((__always_inline__)) \ vst2_lane_ ## funcsuffix (ptrtype *__ptr, \ @@ -9965,31 +9965,37 @@ vst2_lane_ ## funcsuffix (ptrtype *__ptr, \ __temp.val[1] \ = vcombine_##funcsuffix (__b.val[1], \ vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[0], 0); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[1], 1); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[0], 0); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[1], 1); \ __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \ __ptr, __o, __c); \ } -__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v4sf, sf, f32, +__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, v2df, df, f64, +__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64, float64x2_t) -__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v16qi, qi, p8, int8x16_t) -__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v8hi, hi, p16, +__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8, + int8x16_t) +__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v16qi, qi, s8, int8x16_t) -__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v8hi, hi, s16, int16x8_t) -__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v4si, si, s32, int32x4_t) -__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, v2di, di, s64, int64x2_t) -__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v16qi, qi, u8, int8x16_t) -__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v8hi, hi, u16, +__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8, + int8x16_t) +__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v4si, si, u32, +__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, v2di, di, u64, +__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64, + int64x2_t) +__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8, + int8x16_t) +__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16, + int16x8_t) +__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32, + int32x4_t) +__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __ST2_LANE_FUNC @@ -10018,8 +10024,8 @@ __ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16) __ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32) __ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64) -#define __ST3_LANE_FUNC(intype, largetype, ptrtype, \ - mode, ptr_mode, funcsuffix, signedtype) \ +#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode, \ + qmode, ptr_mode, funcsuffix, signedtype) \ __extension__ static __inline void \ __attribute__ ((__always_inline__)) \ vst3_lane_ ## funcsuffix (ptrtype *__ptr, \ @@ -10036,33 +10042,39 @@ vst3_lane_ ## funcsuffix (ptrtype *__ptr, \ __temp.val[2] \ = vcombine_##funcsuffix (__b.val[2], \ vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[0], 0); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[1], 1); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[2], 2); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[0], 0); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[1], 1); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[2], 2); \ __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \ __ptr, __o, __c); \ } -__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v4sf, sf, f32, +__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, v2df, df, f64, +__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64, float64x2_t) -__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v16qi, qi, p8, int8x16_t) -__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v8hi, hi, p16, +__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8, + int8x16_t) +__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16, + int16x8_t) +__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8, + int8x16_t) +__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v16qi, qi, s8, int8x16_t) -__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v8hi, hi, s16, int16x8_t) -__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v4si, si, s32, int32x4_t) -__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, v2di, di, s64, int64x2_t) -__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v16qi, qi, u8, int8x16_t) -__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v8hi, hi, u16, +__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32, + int32x4_t) +__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64, + int64x2_t) +__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8, + int8x16_t) +__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v4si, si, u32, +__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, v2di, di, u64, +__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __ST3_LANE_FUNC @@ -10091,8 +10103,8 @@ __ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16) __ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32) __ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64) -#define __ST4_LANE_FUNC(intype, largetype, ptrtype, \ - mode, ptr_mode, funcsuffix, signedtype) \ +#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode, \ + qmode, ptr_mode, funcsuffix, signedtype) \ __extension__ static __inline void \ __attribute__ ((__always_inline__)) \ vst4_lane_ ## funcsuffix (ptrtype *__ptr, \ @@ -10112,35 +10124,41 @@ vst4_lane_ ## funcsuffix (ptrtype *__ptr, \ __temp.val[3] \ = vcombine_##funcsuffix (__b.val[3], \ vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[0], 0); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[1], 1); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[2], 2); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[3], 3); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[0], 0); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[1], 1); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[2], 2); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[3], 3); \ __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \ __ptr, __o, __c); \ } -__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v4sf, sf, f32, +__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, v2df, df, f64, +__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64, float64x2_t) -__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v16qi, qi, p8, int8x16_t) -__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v8hi, hi, p16, +__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8, + int8x16_t) +__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v16qi, qi, s8, int8x16_t) -__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v8hi, hi, s16, int16x8_t) -__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v4si, si, s32, int32x4_t) -__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, v2di, di, s64, int64x2_t) -__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v16qi, qi, u8, int8x16_t) -__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v8hi, hi, u16, +__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8, + int8x16_t) +__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16, + int16x8_t) +__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32, + int32x4_t) +__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64, + int64x2_t) +__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8, + int8x16_t) +__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v4si, si, u32, +__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, v2di, di, u64, +__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __ST4_LANE_FUNC @@ -16799,8 +16817,8 @@ vld4q_dup_f64 (const float64_t * __a) /* vld2_lane */ -#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, \ - mode, ptrmode, funcsuffix, signedtype) \ +#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode, \ + qmode, ptrmode, funcsuffix, signedtype) \ __extension__ static __inline intype __attribute__ ((__always_inline__)) \ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ { \ @@ -16810,12 +16828,12 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0)); \ __temp.val[1] = \ vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0)); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[0], \ - 0); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[1], \ - 1); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[0], \ + 0); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[1], \ + 1); \ __o = __builtin_aarch64_ld2_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0); \ @@ -16823,29 +16841,29 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ return __b; \ } -__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v4sf, +__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, v2df, +__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df, df, f64, float64x2_t) -__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v16qi, qi, p8, +__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8, int8x16_t) -__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v8hi, hi, +__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v16qi, qi, s8, +__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8, int8x16_t) -__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v8hi, hi, s16, +__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v4si, si, s32, +__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, v2di, di, s64, +__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64, int64x2_t) -__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v16qi, qi, u8, +__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8, int8x16_t) -__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v8hi, hi, +__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v4si, si, +__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, v2di, di, +__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __LD2_LANE_FUNC @@ -16884,8 +16902,8 @@ __LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64) /* vld3_lane */ -#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, \ - mode, ptrmode, funcsuffix, signedtype) \ +#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode, \ + qmode, ptrmode, funcsuffix, signedtype) \ __extension__ static __inline intype __attribute__ ((__always_inline__)) \ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ { \ @@ -16897,15 +16915,15 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0)); \ __temp.val[2] = \ vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0)); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[0], \ - 0); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[1], \ - 1); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[2], \ - 2); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[0], \ + 0); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[1], \ + 1); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[2], \ + 2); \ __o = __builtin_aarch64_ld3_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0); \ @@ -16914,29 +16932,29 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ return __b; \ } -__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v4sf, +__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, v2df, +__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df, df, f64, float64x2_t) -__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v16qi, qi, p8, +__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8, int8x16_t) -__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v8hi, hi, +__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v16qi, qi, s8, +__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8, int8x16_t) -__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v8hi, hi, s16, +__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v4si, si, s32, +__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, v2di, di, s64, +__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64, int64x2_t) -__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v16qi, qi, u8, +__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8, int8x16_t) -__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v8hi, hi, +__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v4si, si, +__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, v2di, di, +__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __LD3_LANE_FUNC @@ -16977,8 +16995,8 @@ __LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64) /* vld4_lane */ -#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, \ - mode, ptrmode, funcsuffix, signedtype) \ +#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode, \ + qmode, ptrmode, funcsuffix, signedtype) \ __extension__ static __inline intype __attribute__ ((__always_inline__)) \ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ { \ @@ -16992,18 +17010,18 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0)); \ __temp.val[3] = \ vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0)); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[0], \ - 0); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[1], \ - 1); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[2], \ - 2); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[3], \ - 3); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[0], \ + 0); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[1], \ + 1); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[2], \ + 2); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[3], \ + 3); \ __o = __builtin_aarch64_ld4_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0); \ @@ -17015,29 +17033,29 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ /* vld4q_lane */ -__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v4sf, +__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, v2df, +__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df, df, f64, float64x2_t) -__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v16qi, qi, p8, +__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8, int8x16_t) -__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v8hi, hi, +__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v16qi, qi, s8, +__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8, int8x16_t) -__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v8hi, hi, s16, +__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v4si, si, s32, +__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, v2di, di, s64, +__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64, int64x2_t) -__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v16qi, qi, u8, +__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8, int8x16_t) -__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v8hi, hi, +__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v4si, si, +__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, v2di, di, +__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __LD4_LANE_FUNC diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c new file mode 100644 index 00000000000..6da45a0ed1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float32x2x2_t +f_vld2_lane_f32 (float32_t * p, float32x2x2_t v) +{ + float32x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c new file mode 100644 index 00000000000..2475b261d78 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float64x1x2_t +f_vld2_lane_f64 (float64_t * p, float64x1x2_t v) +{ + float64x1x2_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld2_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld2_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c new file mode 100644 index 00000000000..f2d26691398 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +poly8x8x2_t +f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v) +{ + poly8x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c new file mode 100644 index 00000000000..0052cfbf20b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int16x4x2_t +f_vld2_lane_s16 (int16_t * p, int16x4x2_t v) +{ + int16x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c new file mode 100644 index 00000000000..19295ce379e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int32x2x2_t +f_vld2_lane_s32 (int32_t * p, int32x2x2_t v) +{ + int32x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c new file mode 100644 index 00000000000..75919012674 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int64x1x2_t +f_vld2_lane_s64 (int64_t * p, int64x1x2_t v) +{ + int64x1x2_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld2_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld2_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c new file mode 100644 index 00000000000..364dde02b8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int8x8x2_t +f_vld2_lane_s8 (int8_t * p, int8x8x2_t v) +{ + int8x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c new file mode 100644 index 00000000000..0e0c159f472 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint16x4x2_t +f_vld2_lane_u16 (uint16_t * p, uint16x4x2_t v) +{ + uint16x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c new file mode 100644 index 00000000000..004318a7cd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint32x2x2_t +f_vld2_lane_u32 (uint32_t * p, uint32x2x2_t v) +{ + uint32x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c new file mode 100644 index 00000000000..a9281c115d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint64x1x2_t +f_vld2_lane_u64 (uint64_t * p, uint64x1x2_t v) +{ + uint64x1x2_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld2_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld2_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c new file mode 100644 index 00000000000..aa9fbff48d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint8x8x2_t +f_vld2_lane_u8 (uint8_t * p, uint8x8x2_t v) +{ + uint8x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c new file mode 100644 index 00000000000..69ff51516eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float32x4x2_t +f_vld2q_lane_f32 (float32_t * p, float32x4x2_t v) +{ + float32x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2q_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c new file mode 100644 index 00000000000..17c9c0c2261 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +float64x2x2_t +f_vld2q_lane_f64 (float64_t * p, float64x2x2_t v) +{ + float64x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2q_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c new file mode 100644 index 00000000000..e1c6fe836e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +poly8x16x2_t +f_vld2q_lane_p8 (poly8_t * p, poly8x16x2_t v) +{ + poly8x16x2_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld2q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld2q_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c new file mode 100644 index 00000000000..3a481a03d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int16x8x2_t +f_vld2q_lane_s16 (int16_t * p, int16x8x2_t v) +{ + int16x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2q_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c new file mode 100644 index 00000000000..aaed314a905 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int32x4x2_t +f_vld2q_lane_s32 (int32_t * p, int32x4x2_t v) +{ + int32x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2q_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c new file mode 100644 index 00000000000..18663c898b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +int64x2x2_t +f_vld2q_lane_s64 (int64_t * p, int64x2x2_t v) +{ + int64x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2q_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c new file mode 100644 index 00000000000..b5db0476c5b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +int8x16x2_t +f_vld2q_lane_s8 (int8_t * p, int8x16x2_t v) +{ + int8x16x2_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld2q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld2q_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c new file mode 100644 index 00000000000..0fb1bd40def --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint16x8x2_t +f_vld2q_lane_u16 (uint16_t * p, uint16x8x2_t v) +{ + uint16x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld2q_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c new file mode 100644 index 00000000000..37ede3f4966 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint32x4x2_t +f_vld2q_lane_u32 (uint32_t * p, uint32x4x2_t v) +{ + uint32x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld2q_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c new file mode 100644 index 00000000000..8390c7c9ca6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +uint64x2x2_t +f_vld2q_lane_u64 (uint64_t * p, uint64x2x2_t v) +{ + uint64x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld2q_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c new file mode 100644 index 00000000000..73c8f26b91c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +uint8x16x2_t +f_vld2q_lane_u8 (uint8_t * p, uint8x16x2_t v) +{ + uint8x16x2_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld2q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld2q_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c new file mode 100644 index 00000000000..303049c44a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float32x2x3_t +f_vld3_lane_f32 (float32_t * p, float32x2x3_t v) +{ + float32x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c new file mode 100644 index 00000000000..3a14e760581 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float64x1x3_t +f_vld3_lane_f64 (float64_t * p, float64x1x3_t v) +{ + float64x1x3_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld3_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld3_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c new file mode 100644 index 00000000000..16ea04a36b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +poly8x8x3_t +f_vld3_lane_p8 (poly8_t * p, poly8x8x3_t v) +{ + poly8x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c new file mode 100644 index 00000000000..e360deb3887 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int16x4x3_t +f_vld3_lane_s16 (int16_t * p, int16x4x3_t v) +{ + int16x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c new file mode 100644 index 00000000000..15e2c08128f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int32x2x3_t +f_vld3_lane_s32 (int32_t * p, int32x2x3_t v) +{ + int32x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c new file mode 100644 index 00000000000..a0d63293ae1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int64x1x3_t +f_vld3_lane_s64 (int64_t * p, int64x1x3_t v) +{ + int64x1x3_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld3_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld3_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c new file mode 100644 index 00000000000..e3ce3af7cce --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int8x8x3_t +f_vld3_lane_s8 (int8_t * p, int8x8x3_t v) +{ + int8x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c new file mode 100644 index 00000000000..2e4f41c6aa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint16x4x3_t +f_vld3_lane_u16 (uint16_t * p, uint16x4x3_t v) +{ + uint16x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c new file mode 100644 index 00000000000..5ad2dc7bf4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint32x2x3_t +f_vld3_lane_u32 (uint32_t * p, uint32x2x3_t v) +{ + uint32x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c new file mode 100644 index 00000000000..2aed64c4c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint64x1x3_t +f_vld3_lane_u64 (uint64_t * p, uint64x1x3_t v) +{ + uint64x1x3_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld3_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld3_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c new file mode 100644 index 00000000000..10d7c17c280 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint8x8x3_t +f_vld3_lane_u8 (uint8_t * p, uint8x8x3_t v) +{ + uint8x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c new file mode 100644 index 00000000000..eb758bb96d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float32x4x3_t +f_vld3q_lane_f32 (float32_t * p, float32x4x3_t v) +{ + float32x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3q_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c new file mode 100644 index 00000000000..6c1100ecc3d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +float64x2x3_t +f_vld3q_lane_f64 (float64_t * p, float64x2x3_t v) +{ + float64x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3q_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c new file mode 100644 index 00000000000..fa585e00fed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +poly8x16x3_t +f_vld3q_lane_p8 (poly8_t * p, poly8x16x3_t v) +{ + poly8x16x3_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld3q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld3q_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c new file mode 100644 index 00000000000..c9d491119ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int16x8x3_t +f_vld3q_lane_s16 (int16_t * p, int16x8x3_t v) +{ + int16x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3q_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c new file mode 100644 index 00000000000..02f33e28f31 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int32x4x3_t +f_vld3q_lane_s32 (int32_t * p, int32x4x3_t v) +{ + int32x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3q_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c new file mode 100644 index 00000000000..57ea88d4315 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +int64x2x3_t +f_vld3q_lane_s64 (int64_t * p, int64x2x3_t v) +{ + int64x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3q_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c new file mode 100644 index 00000000000..43be6b029cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +int8x16x3_t +f_vld3q_lane_s8 (int8_t * p, int8x16x3_t v) +{ + int8x16x3_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld3q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld3q_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c new file mode 100644 index 00000000000..36f922327d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint16x8x3_t +f_vld3q_lane_u16 (uint16_t * p, uint16x8x3_t v) +{ + uint16x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld3q_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c new file mode 100644 index 00000000000..8970951f94d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint32x4x3_t +f_vld3q_lane_u32 (uint32_t * p, uint32x4x3_t v) +{ + uint32x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld3q_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c new file mode 100644 index 00000000000..2874fe1a865 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +uint64x2x3_t +f_vld3q_lane_u64 (uint64_t * p, uint64x2x3_t v) +{ + uint64x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld3q_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c new file mode 100644 index 00000000000..574c7d7ef6e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +uint8x16x3_t +f_vld3q_lane_u8 (uint8_t * p, uint8x16x3_t v) +{ + uint8x16x3_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld3q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld3q_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c new file mode 100644 index 00000000000..dbd76e4d846 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float32x2x4_t +f_vld4_lane_f32 (float32_t * p, float32x2x4_t v) +{ + float32x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c new file mode 100644 index 00000000000..5bdcc45e891 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float64x1x4_t +f_vld4_lane_f64 (float64_t * p, float64x1x4_t v) +{ + float64x1x4_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld4_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld4_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c new file mode 100644 index 00000000000..ab2d3f83e97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +poly8x8x4_t +f_vld4_lane_p8 (poly8_t * p, poly8x8x4_t v) +{ + poly8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c new file mode 100644 index 00000000000..d5b16490abb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int16x4x4_t +f_vld4_lane_s16 (int16_t * p, int16x4x4_t v) +{ + int16x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c new file mode 100644 index 00000000000..2927eaaa2ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int32x2x4_t +f_vld4_lane_s32 (int32_t * p, int32x2x4_t v) +{ + int32x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c new file mode 100644 index 00000000000..43d8ca1e163 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int64x1x4_t +f_vld4_lane_s64 (int64_t * p, int64x1x4_t v) +{ + int64x1x4_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld4_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld4_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c new file mode 100644 index 00000000000..e924275e161 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int8x8x4_t +f_vld4_lane_s8 (int8_t * p, int8x8x4_t v) +{ + int8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c new file mode 100644 index 00000000000..42d479c7d1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint16x4x4_t +f_vld4_lane_u16 (uint16_t * p, uint16x4x4_t v) +{ + uint16x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c new file mode 100644 index 00000000000..d668be3e968 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint32x2x4_t +f_vld4_lane_u32 (uint32_t * p, uint32x2x4_t v) +{ + uint32x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c new file mode 100644 index 00000000000..2348571e2ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint64x1x4_t +f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) +{ + uint64x1x4_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld4_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vld4_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c new file mode 100644 index 00000000000..4bfd28ced44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint8x8x4_t +f_vld4_lane_u8 (uint8_t * p, uint8x8x4_t v) +{ + uint8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c new file mode 100644 index 00000000000..a741fc71860 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +float32x4x4_t +f_vld4q_lane_f32 (float32_t * p, float32x4x4_t v) +{ + float32x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4q_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c new file mode 100644 index 00000000000..d2a230f6cb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +float64x2x4_t +f_vld4q_lane_f64 (float64_t * p, float64x2x4_t v) +{ + float64x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4q_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c new file mode 100644 index 00000000000..a0a129e0606 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +poly8x16x4_t +f_vld4q_lane_p8 (poly8_t * p, poly8x16x4_t v) +{ + poly8x16x4_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld4q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld4q_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c new file mode 100644 index 00000000000..88510e2fa3b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int16x8x4_t +f_vld4q_lane_s16 (int16_t * p, int16x8x4_t v) +{ + int16x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4q_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c new file mode 100644 index 00000000000..398df0732b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +int32x4x4_t +f_vld4q_lane_s32 (int32_t * p, int32x4x4_t v) +{ + int32x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4q_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c new file mode 100644 index 00000000000..974244d5cf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +int64x2x4_t +f_vld4q_lane_s64 (int64_t * p, int64x2x4_t v) +{ + int64x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4q_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c new file mode 100644 index 00000000000..f0a0b1be907 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +int8x16x4_t +f_vld4q_lane_s8 (int8_t * p, int8x16x4_t v) +{ + int8x16x4_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld4q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld4q_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c new file mode 100644 index 00000000000..bf32f2557e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint16x8x4_t +f_vld4q_lane_u16 (uint16_t * p, uint16x8x4_t v) +{ + uint16x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4q_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c new file mode 100644 index 00000000000..7cebb4688f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +uint32x4x4_t +f_vld4q_lane_u32 (uint32_t * p, uint32x4x4_t v) +{ + uint32x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + res = vld4q_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c new file mode 100644 index 00000000000..b8746b9cc81 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +uint64x2x4_t +f_vld4q_lane_u64 (uint64_t * p, uint64x2x4_t v) +{ + uint64x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vld4q_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c new file mode 100644 index 00000000000..a4f1a9b537d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c @@ -0,0 +1,17 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +uint8x16x4_t +f_vld4q_lane_u8 (uint8_t * p, uint8x16x4_t v) +{ + uint8x16x4_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld4q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + res = vld4q_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c new file mode 100644 index 00000000000..a49b0bb4e5f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_f32 (float32_t * p, float32x2x2_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2_lane_f32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c new file mode 100644 index 00000000000..b04b10cd80b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_f64 (float64_t * p, float64x1x2_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst2_lane_f64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst2_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c new file mode 100644 index 00000000000..84c3c0c87b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_p8 (poly8_t * p, poly8x8x2_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2_lane_p8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c new file mode 100644 index 00000000000..eb63c6eee8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_s16 (int16_t * p, int16x4x2_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2_lane_s16 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c new file mode 100644 index 00000000000..b272677c3b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_s32 (int32_t * p, int32x2x2_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2_lane_s32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c new file mode 100644 index 00000000000..43863b41c7e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_s64 (int64_t * p, int64x1x2_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst2_lane_s64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst2_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c new file mode 100644 index 00000000000..c9126dda356 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_s8 (int8_t * p, int8x8x2_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2_lane_s8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c new file mode 100644 index 00000000000..0b088e5daab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_u16 (uint16_t * p, uint16x4x2_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2_lane_u16 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c new file mode 100644 index 00000000000..e15e815d896 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_u32 (uint32_t * p, uint32x2x2_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2_lane_u32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c new file mode 100644 index 00000000000..76450625d56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_u64 (uint64_t * p, uint64x1x2_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst2_lane_u64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst2_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c new file mode 100644 index 00000000000..2f855a7c074 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2_lane_u8 (uint8_t * p, uint8x8x2_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2_lane_u8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c new file mode 100644 index 00000000000..c0031118caa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2q_lane_f32 (float32_t * p, float32x4x2_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2q_lane_f32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2q_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c new file mode 100644 index 00000000000..a7aabe846ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst2q_lane_f64 (float64_t * p, float64x2x2_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2q_lane_f64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2q_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c new file mode 100644 index 00000000000..94a1dc3368f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst2q_lane_p8 (poly8_t * p, poly8x16x2_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst2q_lane_p8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst2q_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c new file mode 100644 index 00000000000..c30faee9242 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2q_lane_s16 (int16_t * p, int16x8x2_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2q_lane_s16 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2q_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c new file mode 100644 index 00000000000..c437bf421b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2q_lane_s32 (int32_t * p, int32x4x2_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2q_lane_s32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2q_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c new file mode 100644 index 00000000000..8f666a3b9b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst2q_lane_s64 (int64_t * p, int64x2x2_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2q_lane_s64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2q_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c new file mode 100644 index 00000000000..b4c98aeae43 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst2q_lane_s8 (int8_t * p, int8x16x2_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst2q_lane_s8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst2q_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c new file mode 100644 index 00000000000..4bfddb9abe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2q_lane_u16 (uint16_t * p, uint16x8x2_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2q_lane_u16 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst2q_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c new file mode 100644 index 00000000000..31db623d59f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst2q_lane_u32 (uint32_t * p, uint32x4x2_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2q_lane_u32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst2q_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c new file mode 100644 index 00000000000..5c73bc4bddd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst2q_lane_u64 (uint64_t * p, uint64x2x2_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2q_lane_u64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst2q_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c new file mode 100644 index 00000000000..8dd8f9724aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst2q_lane_u8 (uint8_t * p, uint8x16x2_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst2q_lane_u8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst2q_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c new file mode 100644 index 00000000000..fd3600ecae9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_f32 (float32_t * p, float32x2x3_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3_lane_f32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c new file mode 100644 index 00000000000..2afc9fd2963 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_f64 (float64_t * p, float64x1x3_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst3_lane_f64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst3_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c new file mode 100644 index 00000000000..779e6486e90 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_p8 (poly8_t * p, poly8x8x3_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3_lane_p8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c new file mode 100644 index 00000000000..1d120a31aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_s16 (int16_t * p, int16x4x3_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3_lane_s16 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c new file mode 100644 index 00000000000..fca05a58ffa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_s32 (int32_t * p, int32x2x3_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3_lane_s32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c new file mode 100644 index 00000000000..f8442bed308 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_s64 (int64_t * p, int64x1x3_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst3_lane_s64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst3_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c new file mode 100644 index 00000000000..cbfde6f4556 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_s8 (int8_t * p, int8x8x3_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3_lane_s8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c new file mode 100644 index 00000000000..d38ffbe2520 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_u16 (uint16_t * p, uint16x4x3_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3_lane_u16 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c new file mode 100644 index 00000000000..d624b256a50 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_u32 (uint32_t * p, uint32x2x3_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3_lane_u32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c new file mode 100644 index 00000000000..59afa96dda3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_u64 (uint64_t * p, uint64x1x3_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst3_lane_u64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst3_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c new file mode 100644 index 00000000000..141120d59dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3_lane_u8 (uint8_t * p, uint8x8x3_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3_lane_u8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c new file mode 100644 index 00000000000..aba3b32f84d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3q_lane_f32 (float32_t * p, float32x4x3_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3q_lane_f32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3q_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c new file mode 100644 index 00000000000..05302f93385 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst3q_lane_f64 (float64_t * p, float64x2x3_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3q_lane_f64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3q_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c new file mode 100644 index 00000000000..b351eca4060 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst3q_lane_p8 (poly8_t * p, poly8x16x3_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst3q_lane_p8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst3q_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c new file mode 100644 index 00000000000..7caa6d261b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3q_lane_s16 (int16_t * p, int16x8x3_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3q_lane_s16 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3q_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c new file mode 100644 index 00000000000..fe01120e8ad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3q_lane_s32 (int32_t * p, int32x4x3_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3q_lane_s32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3q_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c new file mode 100644 index 00000000000..ba4a5cae97a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst3q_lane_s64 (int64_t * p, int64x2x3_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3q_lane_s64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3q_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c new file mode 100644 index 00000000000..b1c601523aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst3q_lane_s8 (int8_t * p, int8x16x3_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst3q_lane_s8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst3q_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c new file mode 100644 index 00000000000..294ff6d7eba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3q_lane_u16 (uint16_t * p, uint16x8x3_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3q_lane_u16 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst3q_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c new file mode 100644 index 00000000000..8817b556a7d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst3q_lane_u32 (uint32_t * p, uint32x4x3_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3q_lane_u32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst3q_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c new file mode 100644 index 00000000000..ce3ef3c42ea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3q_lane_u64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst3q_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c new file mode 100644 index 00000000000..a7fdbe2eebe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst3q_lane_u8 (uint8_t * p, uint8x16x3_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst3q_lane_u8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst3q_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c new file mode 100644 index 00000000000..f89e7900b51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_f32 (float32_t * p, float32x2x4_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4_lane_f32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c new file mode 100644 index 00000000000..6a657f41000 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_f64 (float64_t * p, float64x1x4_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst4_lane_f64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst4_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c new file mode 100644 index 00000000000..19b7712c76f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_p8 (poly8_t * p, poly8x8x4_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4_lane_p8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c new file mode 100644 index 00000000000..422de79eeaa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_s16 (int16_t * p, int16x4x4_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4_lane_s16 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c new file mode 100644 index 00000000000..33431c648ad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_s32 (int32_t * p, int32x2x4_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4_lane_s32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c new file mode 100644 index 00000000000..8f198f7ab26 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_s64 (int64_t * p, int64x1x4_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst4_lane_s64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst4_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c new file mode 100644 index 00000000000..83148062864 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_s8 (int8_t * p, int8x8x4_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4_lane_s8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c new file mode 100644 index 00000000000..b6ed807e233 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_u16 (uint16_t * p, uint16x4x4_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4_lane_u16 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c new file mode 100644 index 00000000000..681a7c0b45d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_u32 (uint32_t * p, uint32x2x4_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4_lane_u32 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c new file mode 100644 index 00000000000..95c69737656 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_u64 (uint64_t * p, uint64x1x4_t v) +{ +/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst4_lane_u64 (p, v, 1); +/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + vst4_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c new file mode 100644 index 00000000000..9e728b41802 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4_lane_u8 (uint8_t * p, uint8x8x4_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4_lane_u8 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c new file mode 100644 index 00000000000..0c6cb618330 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4q_lane_f32 (float32_t * p, float32x4x4_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4q_lane_f32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4q_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c new file mode 100644 index 00000000000..a360e5a594f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst4q_lane_f64 (float64_t * p, float64x2x4_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4q_lane_f64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4q_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c new file mode 100644 index 00000000000..52af012439b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst4q_lane_p8 (poly8_t * p, poly8x16x4_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst4q_lane_p8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst4q_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c new file mode 100644 index 00000000000..a30b0fbc9a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4q_lane_s16 (int16_t * p, int16x8x4_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4q_lane_s16 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4q_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c new file mode 100644 index 00000000000..0b9276aa73f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4q_lane_s32 (int32_t * p, int32x4x4_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4q_lane_s32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4q_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c new file mode 100644 index 00000000000..d7197d52f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst4q_lane_s64 (int64_t * p, int64x2x4_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4q_lane_s64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4q_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c new file mode 100644 index 00000000000..5c285c75382 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst4q_lane_s8 (int8_t * p, int8x16x4_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst4q_lane_s8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst4q_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c new file mode 100644 index 00000000000..9ad7d5257f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4q_lane_u16 (uint16_t * p, uint16x8x4_t v) +{ +/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4q_lane_u16 (p, v, 8); +/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */ + vst4q_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c new file mode 100644 index 00000000000..c3ad0d77fbf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ + +void +f_vst4q_lane_u32 (uint32_t * p, uint32x4x4_t v) +{ +/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4q_lane_u32 (p, v, 4); +/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ + vst4q_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c new file mode 100644 index 00000000000..66fa8a22b7e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst4q_lane_u64 (uint64_t * p, uint64x2x4_t v) +{ +/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4q_lane_u64 (p, v, 2); +/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + vst4q_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c new file mode 100644 index 00000000000..d05fcd89fdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-xfail-if "" { arm-*-* } } */ +/* { dg-skip-if "" { arm-*-* } } */ + +void +f_vst4q_lane_u8 (uint8_t * p, uint8x16x4_t v) +{ +/* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst4q_lane_u8 (p, v, 16); +/* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */ + vst4q_lane_u8 (p, v, -1); + return; +} |