diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2015-12-28 09:50:13 +0100 |
|---|---|---|
| committer | Linaro Code Review <review@review.linaro.org> | 2016-01-12 15:18:34 +0000 |
| commit | a49af31a9eabf698ecf1bbf71dec73d71d67034b (patch) | |
| tree | 5c6aabccf70d167e7536fd8fbea23d8683f416ef | |
| parent | 00e626b91385d0a328eb173c0ded5baeb59222b2 (diff) | |
gcc/
Backport from trunk r231696.
2015-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/68696
* config/aarch64/aarch64-simd.md (*aarch64_simd_bsl<mode>_alt):
New pattern.
(aarch64_simd_bsl<mode>_internal): Update comment to reflect
the above.
Change-Id: I90ba28be8c1fcdf20d127dd1874effba90130221
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7acf7222ccd..7ebca352a40 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2095,6 +2095,10 @@ ;; bit op0, op2, mask ;; if (op0 = op2) (so 0-bits in mask choose bits from op1, else op0) ;; bif op0, op1, mask +;; +;; This pattern is expanded to by the aarch64_simd_bsl<mode> expander. +;; Some forms of straight-line code may generate the equivalent form +;; in *aarch64_simd_bsl<mode>_alt. (define_insn "aarch64_simd_bsl<mode>_internal" [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") @@ -2114,6 +2118,29 @@ [(set_attr "type" "neon_bsl<q>")] ) +;; We need this form in addition to the above pattern to match the case +;; when combine tries merging three insns such that the second operand of +;; the outer XOR matches the second operand of the inner XOR rather than +;; the first. The two are equivalent but since recog doesn't try all +;; permutations of commutative operations, we have to have a separate pattern. + +(define_insn "*aarch64_simd_bsl<mode>_alt" + [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") + (xor:VSDQ_I_DI + (and:VSDQ_I_DI + (xor:VSDQ_I_DI + (match_operand:VSDQ_I_DI 3 "register_operand" "w,w,0") + (match_operand:VSDQ_I_DI 2 "register_operand" "w,0,w")) + (match_operand:VSDQ_I_DI 1 "register_operand" "0,w,w")) + (match_dup:VSDQ_I_DI 2)))] + "TARGET_SIMD" + "@ + bsl\\t%0.<Vbtype>, %3.<Vbtype>, %2.<Vbtype> + bit\\t%0.<Vbtype>, %3.<Vbtype>, %1.<Vbtype> + bif\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" + [(set_attr "type" "neon_bsl<q>")] +) + (define_expand "aarch64_simd_bsl<mode>" [(match_operand:VALLDIF 0 "register_operand") (match_operand:<V_cmp_result> 1 "register_operand") |