diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2015-08-23 22:06:10 +0200 |
|---|---|---|
| committer | Linaro Code Review <review@review.linaro.org> | 2015-08-27 12:45:15 +0000 |
| commit | 3591aa411213def89ff06d296653cf02f9e9cd3c (patch) | |
| tree | 592da5ecdae68a45299eb0b7c802bef48657a473 | |
| parent | a45a61d16c2d0c077d98af4b64a81e4d563f9e88 (diff) | |
gcc/
Backport from trunk r222679.
2015-05-01 Wilco Dijkstra <wdijkstr@arm.com>
* gcc/config/aarch64/aarch64-protos.h (tune_params):
Add min_div_recip_mul_sf and min_div_recip_mul_df fields.
* gcc/config/aarch64/aarch64.c (aarch64_min_divisions_for_recip_mul):
Return value depending on target.
(generic_tunings): Initialize new target settings.
(cortexa53_tunings): Likewise.
(cortexa57_tunings): Likewise.
(thunderx_tunings): Likewise.
(xgene1_tunings): Likewise.
Change-Id: I052cf1a6c9656d952b9b54ca473bdf911d02a127
| -rw-r--r-- | gcc/config/aarch64/aarch64-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 26 |
2 files changed, 21 insertions, 7 deletions
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 232c346573f..931c8b81cc0 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -185,6 +185,8 @@ struct tune_params const int int_reassoc_width; const int fp_reassoc_width; const int vec_reassoc_width; + const int min_div_recip_mul_sf; + const int min_div_recip_mul_df; }; HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5d751d06ecd..af5b4c23975 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -361,7 +361,9 @@ static const struct tune_params generic_tunings = 4, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params cortexa53_tunings = @@ -380,7 +382,9 @@ static const struct tune_params cortexa53_tunings = 4, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params cortexa57_tunings = @@ -399,7 +403,9 @@ static const struct tune_params cortexa57_tunings = 4, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params thunderx_tunings = @@ -417,7 +423,9 @@ static const struct tune_params thunderx_tunings = 8, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params xgene1_tunings = @@ -435,7 +443,9 @@ static const struct tune_params xgene1_tunings = 16, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; /* A processor implementing AArch64. */ @@ -524,9 +534,11 @@ static const char * const aarch64_condition_codes[] = }; static unsigned int -aarch64_min_divisions_for_recip_mul (enum machine_mode mode ATTRIBUTE_UNUSED) +aarch64_min_divisions_for_recip_mul (enum machine_mode mode) { - return 2; + if (GET_MODE_UNIT_SIZE (mode) == 4) + return aarch64_tune_params->min_div_recip_mul_sf; + return aarch64_tune_params->min_div_recip_mul_df; } static int |