Merge from FSF GCC 4.7.1 (svn branches/gcc-4_7-branch 191123).

140 files changed, 3351 insertions, 1011 deletions

diff --git a/ChangeLog b/ChangeLog
index feb54daef03..125f9ec9186 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,12 @@
+2012-09-05  Georg-Johann Lay  <avr@gjlay.de>
+
+	Backport from 2012-09-05 mainline r190697.
+	
+	PR target/54461
+	* configure.ac (noconfigdirs,target=avr-*-*): Add target-newlib,
+	target-libgloss if configured --with-avrlibc.
+	* configure: Regenerate.
+
 2012-06-14  Release Manager
 
 	* GCC 4.7.1 released.
diff --git a/ChangeLog.linaro b/ChangeLog.linaro
index b73f72b66ef..edebd10923f 100644
--- a/ChangeLog.linaro
+++ b/ChangeLog.linaro
@@ -1,5 +1,9 @@
 2012-09-11  Michael Hope  <michael.hope@linaro.org>
 
+	Merge from FSF GCC 4.7.1 (svn branches/gcc-4_7-branch 191123).
+
+2012-09-11  Michael Hope  <michael.hope@linaro.org>
+
 	LP: #1046999
 	Revert:
 
diff --git a/configure b/configure
index 9136c24fbe9..911351626ef 100755
--- a/configure
+++ b/configure
@@ -3447,6 +3447,13 @@ case "${target}" in
   arm-*-riscix*)
     noconfigdirs="$noconfigdirs ld target-libgloss"
     ;;
+  avr-*-rtems*)
+    ;;
+  avr-*-*)
+    if test x${with_avrlibc} = xyes; then
+      noconfigdirs="$noconfigdirs target-newlib target-libgloss"
+    fi
+    ;;
   c4x-*-* | tic4x-*-*)
     noconfigdirs="$noconfigdirs target-libgloss"
     ;;
diff --git a/configure.ac b/configure.ac
index 92e6db39851..40aeeee549b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -873,6 +873,13 @@ case "${target}" in
   arm-*-riscix*)
     noconfigdirs="$noconfigdirs ld target-libgloss"
     ;;
+  avr-*-rtems*)
+    ;;
+  avr-*-*)
+    if test x${with_avrlibc} = xyes; then
+      noconfigdirs="$noconfigdirs target-newlib target-libgloss"
+    fi
+    ;;
   c4x-*-* | tic4x-*-*)
     noconfigdirs="$noconfigdirs target-libgloss"
     ;;
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e368e9a5205..498ff5a9b95 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,9 +1,536 @@
+2012-09-07  Richard Guenther  <rguenther@suse.de>
+
+	Backport from mainline
+	2012-06-26  Jan Hubicka  <jh@suse.cz>
+
+	PR lto/53572
+	* cgraph.h (varpool_can_remove_if_no_refs): Fix handling of
+	used symbols.
+
+2012-09-07  Richard Guenther  <rguenther@suse.de>
+
+	Backport from mainline
+	2012-07-13  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/53922
+	* tree-vrp.c (value_inside_range): Change prototype to take
+	min/max instead of value-range.
+	(range_includes_zero_p): Likewise.  Return the result from
+	value_inside_range.
+	(extract_range_from_binary_expr_1): Adjust to handle dont-know
+	return value from range_includes_zero_p.
+	(extract_range_from_unary_expr_1): Likewise.
+	(compare_range_with_value): Likewise.
+	(vrp_meet_1): Likewise.
+
+2012-09-07  Richard Guenther  <rguenther@suse.de>
+
+	PR middle-end/53667
+	* tree-ssa-structalias.c (handle_rhs_call): Properly clobber
+	EAF_NOESCAPED arguments.  Transitively close non-EAF_DIRECT
+	arguments separately.
+
+2012-09-07  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from mainline
+	2012-09-06  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/54455
+	* sel-sched-ir.c (maybe_tidy_empty_bb): Give up if previous fallthru
+	bb ends up with asm goto referencing bb's label.
+
+2012-09-07  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	Backport from mainline.
+	2012-08-29  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+                   Richard Earnshaw  <richard.earnshaw@arm.com>
+
+	PR target/54252
+	* config/arm/arm.c (neon_dereference_pointer): Adjust nelems by
+	element size. Use elem_type from the formal parameter. New parameter
+	fcode.
+	(neon_expand_args): Adjust call to neon_dereference_pointer.
+
+2012-09-06  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sse.md (<sse4_1_avx2>_pblendvb): Use
+	reg_not_xmm0_operand_maybe_avx as operand 0 constraint.
+
+2012-09-06  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-08-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (isa): Add fma and fma4.
+	(enabled): Handle fma and fma4.
+	* config/i386/sse.md (*fma_fmadd_<mode>): Merge *fma4_fmadd_<mode>.
+	(*fma_fmsub_<mode>): Merge *fma4_fmsub_<mode>.
+	(*fma_fnmadd_<mode>): Merge *fma4_fnmadd_<mode>.
+	(*fma_fnmsub_<mode>): Merge *fma4_fnmsub_<mode>.
+	(*fma_fmaddsub_<mode>): Merge *fma4_fmaddsub_<mode>.
+	(*fma_fmsubadd_<mode>): Merge *fma4_fmsubadd_<mode>.
+
+	2012-08-10  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sse.md (*fma_fmadd_<mode>, *fma_fmsub_<mode>,
+	*fma_fnmadd_<mode>, *fma_fnmsub_<mode>, *fma_fmaddsub_<mode>,
+	*fma_fmsubadd_<mode>): Move FMA3 insn patterns before FMA4 patterns.
+
+2012-09-06  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/54498
+	* tree-ssa-alias.h (get_continuation_for_phi): Add flag to
+	abort when reaching an already visited region.
+	* tree-ssa-alias.c (maybe_skip_until): Likewise.  And do it.
+	(get_continuation_for_phi_1): Likewise.
+	(walk_non_aliased_vuses): When we translated the reference,
+	abort when we re-visit a region.
+	* tree-ssa-pre.c (translate_vuse_through_block): Adjust.
+
+2012-09-06  Andrew Pinski  <apinski@cavium.com>
+
+	PR tree-opt/54494
+	* tree-inline.c (remap_gimple_op_r): Copy TREE_SIDE_EFFECTS also.
+
+2012-09-05  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/54486
+	* builtins.c (fold_builtin_strspn, fold_builtin_strcspn): Use
+	build_int_cst with size_type_node instead of size_int.
+
+2012-09-05  Georg-Johann Lay  <avr@gjlay.de>
+
+	Backport from 2012-09-05 mainline r190697.
+
+	PR target/54461
+	* config.gcc (tm_file,target=avr-*-*): Add avr/avrlibc.h if
+	configured --with-avrlibc.
+	(tm_defines,target=avr-*-*): Add WITH_AVRLIBC if configured
+	--with-avrlibc.
+	* config/avr/avrlibc.h: New file.
+	* config/avr/avr-c.c: Build-in define __WITH_AVRLIBC__ if
+	configured --with-avrlibc.
+	* doc/invoke.texi (AVR Built-in Macros): Document __WITH_AVRLIBC__
+
+2012-09-05  Bin Cheng  <bin.cheng@arm.com>
+
+	Backport from 2012-09-04 mainline r190919
+
+	PR target/45070
+	* config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value
+	of size less than 4 bytes by using macro ARM_NUM_INTS.
+	(thumb1_unexpanded_epilogue): Use macro ARM_NUM_INTS.
+
+2012-09-04  Richard Henderson  <rth@redhat.com>
+
+	* alias.c (read_dependence): Return true for ALIAS_SET_MEMORY_BARRIER.
+
+2012-09-04  Georg-Johann Lay  <avr@gjlay.de>
+
+	Backport from 2012-09-04 mainline r190920
+
+	PR target/54476
+	* config/avr/avr.c (avr_expand_delay_cycles): Mask operand with SImode.
+
+2012-09-04  Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
+
+	Backport from 2012-09-04 mainline r190914
+
+	PR target/54220
+	* config/avr/avr.c (TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS): New
+	define to...
+	(avr_allocate_stack_slots_for_args): ...this new static function.
+
+2012-09-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backported from mainline
+	2012-08-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR driver/54335
+	* doc/invoke.texi: Add -da and remove -dm.
+
+2012-09-03  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from mainline
+	2012-09-01  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/54436
+	* config/i386/i386.md (*mov<mode>_insv_1_rex64, *movsi_insv_1): If
+	operands[1] is CONST_INT_P, convert it to QImode before printing.
+
+	2012-08-31  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/54428
+	* c-convert.c (convert): Don't call fold_convert_loc if
+	TYPE_MAIN_VARIANT of a COMPLEX_TYPE is the same, unless e
+	is a COMPLEX_EXPR.  Remove TYPE_MAIN_VARIANT check from
+	COMPLEX_TYPE -> COMPLEX_TYPE conversion.
+
+	2012-08-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/54363
+	* gimplify.c (optimize_compound_literals_in_ctor): Only recurse
+	if init is a CONSTRUCTOR.
+
+2012-09-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/54369
+	* config/mips/mips.c (mips_reorg): Invoke cleanup_barriers before
+	calling dbr_schedule.
+	* config/sparc/sparc.c (sparc_reorg): Likewise.
+
+2012-08-31  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	Backport from mainline
+	2012-08-23  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+	* config/i386/i386.c (ia32_multipass_dfa_lookahead) : Add
+	case for Atom processor.
+
+2012-08-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-08-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/46254
+	* config/i386/predicates.md (cmpxchg8b_pic_memory_operand): Return
+	true for TARGET_64BIT or !flag_pic.
+	* config/i386/sync.md (*atomic_compare_and_swap_doubledi_pic): Remove.
+	(atomic_compare_and_swap_double<mode>): Change operand 2 predicate
+	to cmpxchg8b_pic_memory_operand.  Use DWIH mode iterator.
+	Add insn constraint.  Conditionally emit xchg asm insns.
+	(atomic_compare_and_swap<mode>): Update calls.  Check only
+	cmpxchg8b_pic_memory_operand in memory address fixup.
+	(DCASMODE): Remove.
+	(CASHMODE): Rename from DCASHMODE.
+	(doublemodesuffix): Update modes.
+	(regprefix): New mode attribute.
+
+	(unspecv) <UNSPECV_CMPXCHG_{1,2,3,4}>: Remove.
+	<UNSPECV_CMPXCHG>: New constant.
+	(atomic_compare_and_swap<mode>_1): Rename from
+	atomic_compare_and_swap_single<mode>.  Update calls and
+	unspec_volatile constants.
+	(atomic_compare_and_swap<mode>_doubleword): Rename from
+	atomic_compare_and_swap_double<mode>.  Update calls and
+	unspec_volatile constants.
+
+2012-08-28  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-28  Walter Lee  <walt@tilera.com>
+
+	* confg/tilegx/tilegx.md: Fix code style.
+	(*zero_extendsidi_truncdisi): Fix typo.
+	* config/tilegx/tilegx.c: Fix code style.
+	(tilegx_function_profiler): Fix typo.
+
+2012-08-27  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-27  Walter Lee  <walt@tilera.com>
+
+	* doc/md.texi (TILE-Gx): Fix typo.
+
+2012-08-27  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-27  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.c (tilegx_function_profiler): Fix typo.
+	* config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
+
+2012-08-27  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-27  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.md (*bfins): Rename to insn_bfins.
+	(insn_bfins): Delete.
+
+2012-08-27  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-27  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/sync.md (atomic_compare_and_swap_bare<mode>,
+	atomic_exchange_bare<mode>,
+	atomic_fetch_<fetchop_name>_bare<mode>): Set type to X1_remote.
+	* config/tilegx/tilegx-generic.md (X1_remote): New insn_reservation.
+	* config/tilegx/tilegx.md (type): Add X1_remove.
+	(insn_cmpexch<four_if_si>, insn_exch<four_if_si>,
+	insn_fetchadd<four_if_si>, insn_fetchaddgez<four_if_si>,
+	insn_fetchand<four_if_si>, insn_fetchor<four_if_si>): Set type to
+	X1_remote.
+
+2012-08-25  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/54088
+	* jump.c (delete_related_insns): Robustify latest change.
+
+2012-08-21  Richard Guenther  <rguenther@suse.de>
+
+	Backport from mainline
+	2012-08-16  Richard Guenther  <rguenther@suse.de>
+
+	PR middle-end/54146
+	* tree-ssa-loop-niter.c (find_loop_niter_by_eval): Free the
+	exit vector.
+	* ipa-pure-const.c (analyze_function): Use FOR_EACH_LOOP_BREAK.
+	* cfgloop.h (FOR_EACH_LOOP_BREAK): Fix.
+	* tree-ssa-structalias.c (handle_lhs_call): Properly free rhsc.
+	* tree-ssa-loop-im.c (analyze_memory_references): Adjust.
+	(tree_ssa_lim_finalize): Free all mem_refs.
+	* tree-ssa-sccvn.c (extract_and_process_scc_for_name): Free
+	scc when bailing out.
+	* modulo-sched.c (sms_schedule): Use FOR_EACH_LOOP_BREAK.
+	* ira-build.c (loop_with_complex_edge_p): Free loop exit vector.
+	* graphite-sese-to-poly.c (scop_ivs_can_be_represented): Use
+	FOR_EACH_LOOP_BREAK.
+
+	2012-08-17  Richard Guenther  <rguenther@suse.de>
+
+	* tree-sra.c (modify_function): Free redirect_callers vector.
+	* ipa-split.c (split_function): Free args_to_pass vector.
+	* tree-vect-stmts.c (vectorizable_operation): Do not pre-allocate
+	vec_oprnds.
+	(new_stmt_vec_info): Do not pre-allocate STMT_VINFO_SAME_ALIGN_REFS.
+	* tree-vect-slp.c (vect_free_slp_instance): Free the instance.
+	(vect_analyze_slp_instance): Free everything.
+	(destroy_bb_vec_info): Free the SLP instances.
+
+	2012-08-17  Richard Guenther  <rguenther@suse.de>
+
+	* params.def (integer-share-limit): Decrease from 256 to 251,
+	add rationale.
+
+	2012-08-21  Richard Guenther  <rguenther@suse.de>
+
+	* tree-ssa-loop-im.c (tree_ssa_lim_finalize): Properly free
+	the affine expansion cache.
+
+2012-08-20  Patrick Marlier  <patrick.marlier@gmail.com>
+
+	Backported from trunk
+	2012-08-20  Patrick Marlier  <patrick.marlier@gmail.com>
+
+	PR middle-end/53992
+	* omp-low.c (lower_omp_1): Handle GIMPLE_TRANSACTION.
+
+2012-08-20  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+	2012-08-15  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/54212
+	* config/arm/neon.md (vec_set<mode>_internal VD,VQ): Do not
+	mark as predicable. Adjust asm template.
+	(vec_setv2di_internal): Likewise.
+	(vec_extract<mode> VD, VQ): Likewise.
+	(vec_extractv2di): Likewise.
+	(neon_vget_lane<mode>_sext_internal VD, VQ): Likewise.
+	(neon_vset_lane<mode>_sext_internal VD, VQ): Likewise.
+	(neon_vdup_n<mode> VX, V32): Likewise.
+	(neon_vdup_nv2di): Likewise.
+
+2012-08-17  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-17  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/feedback.h (FEEDBACK_ENTER_EXPLICIT): Define.
+	(FEEDBACK_ENTER): Define.
+	(FEEDBACK_REENTER): Define.
+	(FEEDBACK_ENTRY): Define.
+	* config/tilepro/feedback.h: (FEEDBACK_ENTER_EXPLICIT): Define.
+	(FEEDBACK_ENTER): Define.
+	(FEEDBACK_REENTER): Define.
+	(FEEDBACK_ENTRY): Define.
+
+2012-08-16  Walter Lee  <walt@tilera.com>
+
+	Backport from mainline
+	2012-08-16  Walter Lee  <walt@tilera.com>
+
+	* config.gcc (tilegx-*-linux*): Add feedback.h.
+	(tilepro-*-linux*): Likewise.
+	* config/tilegx/feedback.h: New file.
+	* config/tilepro/feedback.h: New file.
+
+2012-08-08  Pavel Chupin  <pavel.v.chupin@intel.com>
+
+	Backport from mainline r189840 and r187586:
+	2012-07-25 Sergey Melnikov <sergey.melnikov@intel.com>
+
+	* config/i386/i386.md (stack_protect_set): Disable the pattern
+	for Android since Android libc (bionic) does not provide random
+	value for stack protection guard at gs:0x14. Guard value
+	will be provided from external symbol (default implementation).
+	(stack_protect_set_<mode>): Likewise.
+	(stack_protect_test): Likewise.
+	(stack_protect_test_<mode>): Likewise.
+	* gcc/defaults.h: Define macro TARGET_HAS_BIONIC to 0 - target does
+	not have Bionic by default
+	* config/linux.h: Redefine macro TARGET_HAS_BIONIC to (OPTION_BIONIC)
+	Macro OPTION_BIONIC is defined in this file and provides Bionic
+	accessibility status
+
+	2012-05-16  Igor Zamyatin  <igor.zamyatin@intel.com>
+
+	* configure.ac: Stack protector enabling for Android targets.
+	* configure: Regenerate.
+
+2012-08-13  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from trunk
+	2012-07-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/53942
+	* function.c (assign_parm_setup_reg): Avoid zero/sign extension
+	directly from likely spilled non-fixed hard registers, move them
+	to pseudo first.
+
+2012-08-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sse.md (xop_phaddbq):  Fix vec_select selectors.
+	(xop_phaddubq): Ditto.
+
+2012-08-10  Ulrich Weigand  <ulrich.weigand@linaro.org>
+
+	Backport from mainline
+	2012-07-30  Ulrich Weigand  <ulrich.weigand@linaro.org>
+		    Richard Earnshaw  <rearnsha@arm.com>
+
+	* target.def (vector_alignment): New target hook.
+	* doc/tm.texi.in (TARGET_VECTOR_ALIGNMENT): Document new hook.
+	* doc/tm.texi: Regenerate.
+	* targhooks.c (default_vector_alignment): New function.
+	* targhooks.h (default_vector_alignment): Add prototype.
+	* stor-layout.c (layout_type): Use targetm.vector_alignment.
+	* config/arm/arm.c (arm_vector_alignment): New function.
+	(TARGET_VECTOR_ALIGNMENT): Define.
+
+	* tree-vect-data-refs.c (vect_update_misalignment_for_peel): Use
+	vector type alignment instead of size.
+	* tree-vect-loop-manip.c (vect_do_peeling_for_loop_bound): Use
+	element type size directly instead of computing it from alignment.
+	Fix variable naming and comment.
+
+2012-08-09  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-08-09  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/alpha/alpha.c (alpha_pad_noreturn): Rename to ...
+	(alpha_pad_function_end): ... this.  Also insert NOP between
+	sibling call and GP load.
+	(alpha_reorg): Update call to alpha_pad_function_end.  Expand comment.
+
+2012-08-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from mainline
+	2012-08-08  Richard Sandiford  <rdsandiford@googlemail.com>
+		    H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR rtl-optimization/54157
+	* combine.c (gen_lowpart_for_combine): Don't return identity
+	for CONST or symbolic reference.
+
+2012-08-06  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-07-23  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386-protos.h (ix86_lea_outperforms): Remove prototype.
+	* config/i386/i386.c (ix86_lea_outperforms): Make static.  Make
+	split_cost argument signed.
+	(ix86_use_lea_for_mov): Use INVALID_REGNUM instead of -1.
+	(ix86_avoid_lea_for_addr): Ditto.
+
+	2012-07-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_avoid_lea_for_addr): Return false if
+	the address has less than two components.
+
+2012-08-02  Steve Ellcey  <sellcey@mips.com>
+
+	Backport from mainline
+	2012-07-19  Steve Ellcey  <sellcey@mips.com>
+
+	* config/mips/mips.c (mips_set_mips16_mode): Clear SYNCI_MASK in
+	MIPS16 mode.
+
+2012-08-02  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-07-24  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/53961
+	* config/i386/i386.c (ix86_legitimate_address_p): Move check for
+	negative constant address for TARGET_X32 ...
+	(ix86_decompose_address): ... here.  Reject constant addresses
+	that don't satisfy x86_64_immediate_operand predicate.
+
+	2012-07-23  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/53961
+	* config/i386/i386.md (*lea): Add asserts to detect invalid addresses.
+	* config/i386/i386.c (ix86_print_operand_address): Ditto.
+	(ix86_decompose_address): Allow (zero_extend:DI (subreg:SI (...)))
+	addresses.  Prevent zero extensions of CONST_INT operands.
+
+	2012-07-22  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/53961
+	* config/i386/i386.md (*lea): New insn pattern.
+	(*lea_1): Remove.
+	(*lea<mode>_2): Ditto.
+	(*lea_{3,4,5,6}_zext): Ditto.
+	* config/i386/predicates.md (lea_address_operand): Do not reject
+	zero-extended address operands.
+	* config/i386/constraints.md (j): Remove address constraint.
+	* config/i386/i386.c (ix86_decompose_address): Allow SImode subreg
+	of an address.
+	(ix86_print_operand_address): Handle SImode subreg of an address.
+	(ix86_avoid_lea_for_addr): Reject zero-extended addresses for now.
+
+2012-08-01  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-03-09  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/52530
+	* config/i386/i386.c (ix86_print_operand): Handle 'E' operand modifier.
+	(ix86_print_operand_address): Handle UNSPEC_LEA_ADDR. Do not fallback
+	to set code to 'q'.
+	* config/i386/i386.md (UNSPEC_LEA_ADDR): New unspec.
+	(*movdi_internal_rex64): Use %E operand modifier for lea.
+	(*movsi_internal): Ditto.
+	(*lea_1): Ditto.
+	(*lea<mode>_2): Ditto.
+	(*lea_{3,4,5,6}_zext): Ditto.
+	(*tls_global_dynamic_32_gnu): Ditto.
+	(*tls_global_dynamic_64): Ditto.
+	(*tls_dynamic_gnu2_lea_32): Ditto.
+	(*tls_dynamic_gnu2_lea_64): Ditto.
+	(pro_epilogue_adjust_stack_<mode>_add): Ditto.
+
+2012-08-01  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-08-01  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_address_subreg_operand): Reject
+	stack pointer.
+	(ix86_print_operand_address): Assert that parts.base and parts.index
+	are non-NULL after call to simplify_subreg.
+
 2012-07-22  Oleg Endo  <olegendo@gcc.gnu.org>
 
 	PR target/33135
 	* config/sh/sh.opt (mieee): Use Var instead of Mask.  Correct
 	description.
-	* config/sh/sh.c (sh_option_override): Do not change 
+	* config/sh/sh.c (sh_option_override): Do not change
 	flag_finite_math_only.  Set TARGET_IEEE to complement of
 	flag_finite_math_only.
 	* doc/invoke.texi (SH options): Add mno-ieee.  Correct
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 143b3f8b047..79162bbf649 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20120731
+20120910
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 3d0fa9b47a2..a9c8f019337 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,8 @@
+2012-09-07  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc-interface/trans.c (Loop_Statement_to_gnu): Revert to using
+	size_type_node instead of sizetype.
+
 2012-07-19  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gcc-interface/decl.c (gnat_to_gnu_entity) <object>: Try to ensure
diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c
index 50e86924510..61648c5664d 100644
--- a/gcc/ada/gcc-interface/trans.c
+++ b/gcc/ada/gcc-interface/trans.c
@@ -2396,14 +2396,15 @@ Loop_Statement_to_gnu (Node_Id gnat_node)
 
 	  /* Otherwise, use the do-while form with the help of a special
 	     induction variable in the unsigned version of the base type
-	     or the unsigned version of sizetype, whichever is the
+	     or the unsigned version of the size type, whichever is the
 	     largest, in order to have wrap-around arithmetics for it.  */
 	  else
 	    {
-	      if (TYPE_PRECISION (gnu_base_type) > TYPE_PRECISION (sizetype))
+	      if (TYPE_PRECISION (gnu_base_type)
+		  > TYPE_PRECISION (size_type_node))
 		gnu_base_type = gnat_unsigned_type (gnu_base_type);
 	      else
-		gnu_base_type = sizetype;
+		gnu_base_type = size_type_node;
 
 	      gnu_first = convert (gnu_base_type, gnu_first);
 	      gnu_last = convert (gnu_base_type, gnu_last);
diff --git a/gcc/alias.c b/gcc/alias.c
index e9d701f9636..f20716d0dff 100644
--- a/gcc/alias.c
+++ b/gcc/alias.c
@@ -2127,12 +2127,18 @@ memrefs_conflict_p (int xsize, rtx x, int ysize, rtx y, HOST_WIDE_INT c)
    storeqi_unaligned pattern.  */
 
 /* Read dependence: X is read after read in MEM takes place.  There can
-   only be a dependence here if both reads are volatile.  */
+   only be a dependence here if both reads are volatile, or if either is
+   an explicit barrier.  */
 
 int
 read_dependence (const_rtx mem, const_rtx x)
 {
-  return MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem);
+  if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
+    return true;
+  if (MEM_ALIAS_SET (x) == ALIAS_SET_MEMORY_BARRIER
+      || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
+    return true;
+  return false;
 }
 
 /* Returns nonzero if something about the mode or address format MEM1
diff --git a/gcc/builtins.c b/gcc/builtins.c
index a086a8cb1a5..04980ccad55 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -11927,7 +11927,7 @@ fold_builtin_strspn (location_t loc, tree s1, tree s2)
       if (p1 && p2)
 	{
 	  const size_t r = strspn (p1, p2);
-	  return size_int (r);
+	  return build_int_cst (size_type_node, r);
 	}
 
       /* If either argument is "", return NULL_TREE.  */
@@ -11972,7 +11972,7 @@ fold_builtin_strcspn (location_t loc, tree s1, tree s2)
       if (p1 && p2)
 	{
 	  const size_t r = strcspn (p1, p2);
-	  return size_int (r);
+	  return build_int_cst (size_type_node, r);
 	}
 
       /* If the first argument is "", return NULL_TREE.  */
diff --git a/gcc/c-convert.c b/gcc/c-convert.c
index f4583c549c9..48d73757653 100644
--- a/gcc/c-convert.c
+++ b/gcc/c-convert.c
@@ -1,6 +1,6 @@
 /* Language-level data type conversion for GNU C.
    Copyright (C) 1987, 1988, 1991, 1998, 2002, 2003, 2004, 2005, 2007, 2008,
-   2009, 2010 Free Software Foundation, Inc.
+   2009, 2010, 2011, 2012 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -92,7 +92,9 @@ convert (tree type, tree expr)
 
   STRIP_TYPE_NOPS (e);
 
-  if (TYPE_MAIN_VARIANT (type) == TYPE_MAIN_VARIANT (TREE_TYPE (expr)))
+  if (TYPE_MAIN_VARIANT (type) == TYPE_MAIN_VARIANT (TREE_TYPE (expr))
+      && (TREE_CODE (TREE_TYPE (expr)) != COMPLEX_TYPE
+	  || TREE_CODE (e) == COMPLEX_EXPR))
     return fold_convert_loc (loc, type, expr);
   if (TREE_CODE (TREE_TYPE (expr)) == ERROR_MARK)
     return error_mark_node;
@@ -135,24 +137,23 @@ convert (tree type, tree expr)
 	 but for the C FE c_save_expr needs to be called instead.  */
       if (TREE_CODE (TREE_TYPE (e)) == COMPLEX_TYPE)
 	{
-	  tree subtype = TREE_TYPE (type);
-	  tree elt_type = TREE_TYPE (TREE_TYPE (e));
-
-	  if (TYPE_MAIN_VARIANT (elt_type) != TYPE_MAIN_VARIANT (subtype)
-	      && TREE_CODE (e) != COMPLEX_EXPR)
+	  if (TREE_CODE (e) != COMPLEX_EXPR)
 	    {
+	      tree subtype = TREE_TYPE (type);
+	      tree elt_type = TREE_TYPE (TREE_TYPE (e));
+
 	      if (in_late_binary_op)
 		e = save_expr (e);
 	      else
 		e = c_save_expr (e);
 	      ret
-		= fold_build2 (COMPLEX_EXPR, type,
-			       convert (subtype,
-					fold_build1 (REALPART_EXPR,
-						     elt_type, e)),
-			       convert (subtype,
-					fold_build1 (IMAGPART_EXPR,
-						     elt_type, e)));
+		= fold_build2_loc (loc, COMPLEX_EXPR, type,
+				   convert (subtype,
+					    fold_build1 (REALPART_EXPR,
+							 elt_type, e)),
+				   convert (subtype,
+					    fold_build1 (IMAGPART_EXPR,
+							 elt_type, e)));
 	      goto maybe_fold;
 	    }
 	}
diff --git a/gcc/cfgloop.h b/gcc/cfgloop.h
index 510bc10bd4a..7573ff4b3af 100644
--- a/gcc/cfgloop.h
+++ b/gcc/cfgloop.h
@@ -629,7 +629,7 @@ fel_init (loop_iterator *li, loop_p *loop, unsigned flags)
 
 #define FOR_EACH_LOOP_BREAK(LI) \
   { \
-    VEC_free (int, heap, (LI)->to_visit); \
+    VEC_free (int, heap, (LI).to_visit); \
     break; \
   }
 
diff --git a/gcc/cgraph.h b/gcc/cgraph.h
index 191364ca377..dfdafd8cc09 100644
--- a/gcc/cgraph.h
+++ b/gcc/cgraph.h
@@ -946,10 +946,13 @@ cgraph_only_called_directly_or_aliased_p (struct cgraph_node *node)
 static inline bool
 varpool_can_remove_if_no_refs (struct varpool_node *node)
 {
+  if (DECL_EXTERNAL (node->decl))
+    return true;
   return (!node->force_output && !node->used_from_other_partition
-	  && (flag_toplevel_reorder || DECL_COMDAT (node->decl)
-	      || DECL_ARTIFICIAL (node->decl))
-  	  && (DECL_COMDAT (node->decl) || !node->externally_visible));
+	  && ((DECL_COMDAT (node->decl)
+	       && !varpool_used_from_object_file_p (node))
+	      || !node->externally_visible
+	      || DECL_HAS_VALUE_EXPR_P (node->decl)));
 }
 
 /* Return true when all references to VNODE must be visible in ipa_ref_list.
diff --git a/gcc/combine.c b/gcc/combine.c
index 976ef77fc53..cd11b29f138 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -10788,13 +10788,6 @@ gen_lowpart_for_combine (enum machine_mode omode, rtx x)
   if (omode == imode)
     return x;
 
-  /* Return identity if this is a CONST or symbolic reference.  */
-  if (omode == Pmode
-      && (GET_CODE (x) == CONST
-	  || GET_CODE (x) == SYMBOL_REF
-	  || GET_CODE (x) == LABEL_REF))
-    return x;
-
   /* We can only support MODE being wider than a word if X is a
      constant integer or has a mode the same size.  */
   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 536e4d66b41..0034c26d2d2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -941,6 +941,10 @@ avr-*-rtems*)
 	;;
 avr-*-*)
 	tm_file="elfos.h avr/elf.h avr/avr.h dbxelf.h avr/avr-stdint.h"
+	if test x${with_avrlibc} = xyes; then
+	    tm_file="${tm_file} ${cpu_type}/avrlibc.h"
+	    tm_defines="${tm_defines} WITH_AVRLIBC"
+	fi
 	tmake_file="avr/t-avr avr/t-multilib"
 	use_gcc_stdint=wrap
 	extra_gcc_objs="driver-avr.o avr-devices.o"
@@ -2514,6 +2518,7 @@ tilegx-*-linux*)
 	extra_objs="mul-tables.o"
 	c_target_objs="tilegx-c.o"
 	cxx_target_objs="tilegx-c.o"
+	extra_headers="feedback.h"
 	;;
 tilepro-*-linux*)
 	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h tilepro/linux.h ${tm_file}"
@@ -2521,6 +2526,7 @@ tilepro-*-linux*)
 	extra_objs="mul-tables.o"
 	c_target_objs="tilepro-c.o"
 	cxx_target_objs="tilepro-c.o"
+	extra_headers="feedback.h"
 	;;
 v850-*-rtems*)
 	target_cpu_default="TARGET_CPU_generic"
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 845b0f160b8..f27c08a8cf8 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -9310,17 +9310,18 @@ alpha_align_insns (unsigned int max_align,
     }
 }
 
-/* Insert an unop between a noreturn function call and GP load.  */
+/* Insert an unop between sibcall or noreturn function call and GP load.  */
 
 static void
-alpha_pad_noreturn (void)
+alpha_pad_function_end (void)
 {
   rtx insn, next;
 
   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
     {
       if (! (CALL_P (insn)
-	     && find_reg_note (insn, REG_NORETURN, NULL_RTX)))
+	     && (SIBLING_CALL_P (insn)
+		 || find_reg_note (insn, REG_NORETURN, NULL_RTX))))
         continue;
 
       /* Make sure we do not split a call and its corresponding
@@ -9352,8 +9353,28 @@ alpha_pad_noreturn (void)
 static void
 alpha_reorg (void)
 {
-  /* Workaround for a linker error that triggers when an
-     exception handler immediatelly follows a noreturn function.
+  /* Workaround for a linker error that triggers when an exception
+     handler immediatelly follows a sibcall or a noreturn function.
+
+In the sibcall case:
+
+     The instruction stream from an object file:
+
+ 1d8:   00 00 fb 6b     jmp     (t12)
+ 1dc:   00 00 ba 27     ldah    gp,0(ra)
+ 1e0:   00 00 bd 23     lda     gp,0(gp)
+ 1e4:   00 00 7d a7     ldq     t12,0(gp)
+ 1e8:   00 40 5b 6b     jsr     ra,(t12),1ec <__funcZ+0x1ec>
+
+     was converted in the final link pass to:
+
+   12003aa88:   67 fa ff c3     br      120039428 <...>
+   12003aa8c:   00 00 fe 2f     unop
+   12003aa90:   00 00 fe 2f     unop
+   12003aa94:   48 83 7d a7     ldq     t12,-31928(gp)
+   12003aa98:   00 40 5b 6b     jsr     ra,(t12),12003aa9c <__func+0x1ec>
+
+And in the noreturn case:
 
      The instruction stream from an object file:
 
@@ -9373,11 +9394,11 @@ alpha_reorg (void)
 
      GP load instructions were wrongly cleared by the linker relaxation
      pass.  This workaround prevents removal of GP loads by inserting
-     an unop instruction between a noreturn function call and
+     an unop instruction between a sibcall or noreturn function call and
      exception handler prologue.  */
 
   if (current_function_has_exception_handlers ())
-    alpha_pad_noreturn ();
+    alpha_pad_function_end ();
 
   if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
     alpha_handle_trap_shadows ();
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 25f4430d68a..5ba6e94e41f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -20807,12 +20807,13 @@ typedef enum {
    and return an expression for the accessed memory.
 
    The intrinsic function operates on a block of registers that has
-   mode REG_MODE.  This block contains vectors of type TYPE_MODE.
-   The function references the memory at EXP in mode MEM_MODE;
-   this mode may be BLKmode if no more suitable mode is available.  */
+   mode REG_MODE.  This block contains vectors of type TYPE_MODE.  The
+   function references the memory at EXP of type TYPE and in mode
+   MEM_MODE; this mode may be BLKmode if no more suitable mode is
+   available.  */
 
 static tree
-neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
+neon_dereference_pointer (tree exp, tree type, enum machine_mode mem_mode,
 			  enum machine_mode reg_mode,
 			  neon_builtin_type_mode type_mode)
 {
@@ -20830,18 +20831,18 @@ neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
   gcc_assert (reg_size % vector_size == 0);
   nvectors = reg_size / vector_size;
 
+  /* Work out the type of each element.  */
+  gcc_assert (POINTER_TYPE_P (type));
+  elem_type = TREE_TYPE (type);
+
   /* Work out how many elements are being loaded or stored.
      MEM_MODE == REG_MODE implies a one-to-one mapping between register
      and memory elements; anything else implies a lane load or store.  */
   if (mem_mode == reg_mode)
-    nelems = vector_size * nvectors;
+    nelems = vector_size * nvectors / int_size_in_bytes (elem_type);
   else
     nelems = nvectors;
 
-  /* Work out the type of each element.  */
-  gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
-  elem_type = TREE_TYPE (TREE_TYPE (exp));
-
   /* Create a type that describes the full access.  */
   upper_bound = build_int_cst (size_type_node, nelems - 1);
   array_type = build_array_type (elem_type, build_index_type (upper_bound));
@@ -20855,12 +20856,14 @@ neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
 static rtx
 arm_expand_neon_args (rtx target, int icode, int have_retval,
 		      neon_builtin_type_mode type_mode,
-		      tree exp, ...)
+		      tree exp, int fcode, ...)
 {
   va_list ap;
   rtx pat;
   tree arg[NEON_MAX_BUILTIN_ARGS];
   rtx op[NEON_MAX_BUILTIN_ARGS];
+  tree arg_type;
+  tree formals;
   enum machine_mode tmode = insn_data[icode].operand[0].mode;
   enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
   enum machine_mode other_mode;
@@ -20873,7 +20876,9 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
 	  || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
     target = gen_reg_rtx (tmode);
 
-  va_start (ap, exp);
+  va_start (ap, fcode);
+
+  formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
 
   for (;;)
     {
@@ -20886,12 +20891,15 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
           opno = argc + have_retval;
           mode[argc] = insn_data[icode].operand[opno].mode;
           arg[argc] = CALL_EXPR_ARG (exp, argc);
+	  arg_type = TREE_VALUE (formals);
           if (thisarg == NEON_ARG_MEMORY)
             {
               other_mode = insn_data[icode].operand[1 - opno].mode;
-              arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
-                                                    other_mode, type_mode);
+              arg[argc] = neon_dereference_pointer (arg[argc], arg_type,
+						    mode[argc], other_mode,
+						    type_mode);
             }
+
           op[argc] = expand_normal (arg[argc]);
 
           switch (thisarg)
@@ -20928,6 +20936,7 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
             }
 
           argc++;
+	  formals = TREE_CHAIN (formals);
         }
     }
 
@@ -21010,7 +21019,7 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
     case NEON_UNOP:
     case NEON_CONVERT:
     case NEON_DUPLANE:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
 
     case NEON_BINOP:
@@ -21020,89 +21029,89 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
     case NEON_SCALARMULH:
     case NEON_SHIFTINSERT:
     case NEON_LOGICBINOP:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
         NEON_ARG_STOP);
 
     case NEON_TERNOP:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
         NEON_ARG_CONSTANT, NEON_ARG_STOP);
 
     case NEON_GETLANE:
     case NEON_FIXCONV:
     case NEON_SHIFTIMM:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
         NEON_ARG_STOP);
 
     case NEON_CREATE:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
 
     case NEON_DUP:
     case NEON_SPLIT:
     case NEON_REINTERP:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
 
     case NEON_COMBINE:
     case NEON_VTBL:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
 
     case NEON_RESULTPAIR:
-      return arm_expand_neon_args (target, icode, 0, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
         NEON_ARG_STOP);
 
     case NEON_LANEMUL:
     case NEON_LANEMULL:
     case NEON_LANEMULH:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
         NEON_ARG_CONSTANT, NEON_ARG_STOP);
 
     case NEON_LANEMAC:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
         NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
 
     case NEON_SHIFTACC:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
         NEON_ARG_CONSTANT, NEON_ARG_STOP);
 
     case NEON_SCALARMAC:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
         NEON_ARG_CONSTANT, NEON_ARG_STOP);
 
     case NEON_SELECT:
     case NEON_VTBX:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
         NEON_ARG_STOP);
 
     case NEON_LOAD1:
     case NEON_LOADSTRUCT:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
 	NEON_ARG_MEMORY, NEON_ARG_STOP);
 
     case NEON_LOAD1LANE:
     case NEON_LOADSTRUCTLANE:
-      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
 	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
 	NEON_ARG_STOP);
 
     case NEON_STORE1:
     case NEON_STORESTRUCT:
-      return arm_expand_neon_args (target, icode, 0, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
 	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
 
     case NEON_STORE1LANE:
     case NEON_STORESTRUCTLANE:
-      return arm_expand_neon_args (target, icode, 0, type_mode, exp,
+      return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
 	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
 	NEON_ARG_STOP);
     }
@@ -22017,7 +22026,7 @@ thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue)
   unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff);
   /* Then count how many other high registers will need to be pushed.  */
   unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
-  int n_free, reg_base;
+  int n_free, reg_base, size;
 
   if (!for_prologue && frame_pointer_needed)
     amount = offsets->locals_base - offsets->saved_regs;
@@ -22056,7 +22065,8 @@ thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue)
   n_free = 0;
   if (!for_prologue)
     {
-      reg_base = arm_size_return_regs () / UNITS_PER_WORD;
+      size = arm_size_return_regs ();
+      reg_base = ARM_NUM_INTS (size);
       live_regs_mask >>= reg_base;
     }
 
@@ -22110,8 +22120,7 @@ thumb_unexpanded_epilogue (void)
   if (extra_pop > 0)
     {
       unsigned long extra_mask = (1 << extra_pop) - 1;
-      live_regs_mask |= extra_mask << ((size + UNITS_PER_WORD - 1) 
-				       / UNITS_PER_WORD);
+      live_regs_mask |= extra_mask << ARM_NUM_INTS (size);
     }
 
   /* The prolog may have pushed some high registers to use as
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index c5cc5a7fa9f..bab4f7bca69 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -435,10 +435,9 @@
     elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
   operands[2] = GEN_INT (elt);
   
-  return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
+  return "vmov.<V_sz_elem>\t%P0[%c2], %1";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_mcr")])
+  [(set_attr "neon_type" "neon_mcr")])
 
 (define_insn "vec_set<mode>_internal"
   [(set (match_operand:VQ 0 "s_register_operand" "=w")
@@ -461,10 +460,9 @@
   operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
   operands[2] = GEN_INT (elt);
 
-  return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
+  return "vmov.<V_sz_elem>\t%P0[%c2], %1";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_mcr")]
+  [(set_attr "neon_type" "neon_mcr")]
 )
 
 (define_insn "vec_setv2di_internal"
@@ -481,10 +479,9 @@
 
   operands[0] = gen_rtx_REG (DImode, regno);
 
-  return "vmov%?\t%P0, %Q1, %R1";
+  return "vmov\t%P0, %Q1, %R1";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_mcr_2_mcrr")]
+  [(set_attr "neon_type" "neon_mcr_2_mcrr")]
 )
 
 (define_expand "vec_set<mode>"
@@ -512,10 +509,9 @@
       elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
       operands[2] = GEN_INT (elt);
     }
-  return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
+  return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_insn "vec_extract<mode>"
@@ -536,10 +532,9 @@
   operands[1] = gen_rtx_REG (<V_HALF>mode, regno + hi);
   operands[2] = GEN_INT (elt);
 
-  return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
+  return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_insn "vec_extractv2di"
@@ -553,10 +548,9 @@
 
   operands[1] = gen_rtx_REG (DImode, regno);
 
-  return "vmov%?\t%Q0, %R0, %P1  @ v2di";
+  return "vmov\t%Q0, %R0, %P1  @ v2di";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_int_1")]
+  [(set_attr "neon_type" "neon_int_1")]
 )
 
 (define_expand "vec_init<mode>"
@@ -2623,10 +2617,9 @@
       elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
       operands[2] = GEN_INT (elt);
     }
-  return "vmov%?.s<V_sz_elem>\t%0, %P1[%c2]";
+  return "vmov.s<V_sz_elem>\t%0, %P1[%c2]";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_insn "neon_vget_lane<mode>_zext_internal"
@@ -2643,10 +2636,9 @@
       elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
       operands[2] = GEN_INT (elt);
     }
-  return "vmov%?.u<V_sz_elem>\t%0, %P1[%c2]";
+  return "vmov.u<V_sz_elem>\t%0, %P1[%c2]";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_insn "neon_vget_lane<mode>_sext_internal"
@@ -2669,12 +2661,11 @@
   ops[0] = operands[0];
   ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
   ops[2] = GEN_INT (elt_adj);
-  output_asm_insn ("vmov%?.s<V_sz_elem>\t%0, %P1[%c2]", ops);
+  output_asm_insn ("vmov.s<V_sz_elem>\t%0, %P1[%c2]", ops);
 
   return "";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_insn "neon_vget_lane<mode>_zext_internal"
@@ -2697,12 +2688,11 @@
   ops[0] = operands[0];
   ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
   ops[2] = GEN_INT (elt_adj);
-  output_asm_insn ("vmov%?.u<V_sz_elem>\t%0, %P1[%c2]", ops);
+  output_asm_insn ("vmov.u<V_sz_elem>\t%0, %P1[%c2]", ops);
 
   return "";
 }
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_expand "neon_vget_lane<mode>"
@@ -2833,10 +2823,9 @@
   [(set (match_operand:VX 0 "s_register_operand" "=w")
         (vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))]
   "TARGET_NEON"
-  "vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
+  "vdup.<V_sz_elem>\t%<V_reg>0, %1"
   ;; Assume this schedules like vmov.
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_insn "neon_vdup_n<mode>"
@@ -2844,11 +2833,10 @@
         (vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))]
   "TARGET_NEON"
   "@
-  vdup%?.<V_sz_elem>\t%<V_reg>0, %1
-  vdup%?.<V_sz_elem>\t%<V_reg>0, %y1"
+  vdup.<V_sz_elem>\t%<V_reg>0, %1
+  vdup.<V_sz_elem>\t%<V_reg>0, %y1"
   ;; Assume this schedules like vmov.
-  [(set_attr "predicable" "yes")
-   (set_attr "neon_type" "neon_bp_simple")]
+  [(set_attr "neon_type" "neon_bp_simple")]
 )
 
 (define_expand "neon_vdup_ndi"
@@ -2866,10 +2854,9 @@
         (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))]
   "TARGET_NEON"
   "@
-  vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1
-  vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1"
-  [(set_attr "predicable" "yes")
-   (set_attr "length" "8")
+  vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1
+  vmov\t%e0, %P1\;vmov\t%f0, %P1"
+  [(set_attr "length" "8")
    (set_attr "neon_type" "neon_bp_simple")]
 )
 
diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c
index d689fa02380..6eb0ebaed5a 100644
--- a/gcc/config/avr/avr-c.c
+++ b/gcc/config/avr/avr-c.c
@@ -148,6 +148,10 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
   cpp_define_formatted (pfile, "__AVR_SFR_OFFSET__=0x%x",
                         avr_current_arch->sfr_offset);
     
+#ifdef WITH_AVRLIBC
+  cpp_define (pfile, "__WITH_AVRLIBC__");
+#endif /* WITH_AVRLIBC */
+      
   /* Define builtin macros so that the user can easily query if or if not
      non-generic address spaces (and which) are supported.
      This is only supported for C.  For C++, a language extension is needed
diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c
index 50682f29690..a95ae30f45f 100644
--- a/gcc/config/avr/avr.c
+++ b/gcc/config/avr/avr.c
@@ -674,6 +674,16 @@ avr_regs_to_save (HARD_REG_SET *set)
   return count;
 }
 
+
+/* Implement `TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS' */
+
+static bool
+avr_allocate_stack_slots_for_args (void)
+{
+  return !cfun->machine->is_naked;
+}
+
+
 /* Return true if register FROM can be eliminated via register TO.  */
 
 static bool
@@ -9916,7 +9926,7 @@ avr_mem_clobber (void)
 static void
 avr_expand_delay_cycles (rtx operands0)
 {
-  unsigned HOST_WIDE_INT cycles = UINTVAL (operands0);
+  unsigned HOST_WIDE_INT cycles = UINTVAL (operands0) & GET_MODE_MASK (SImode);
   unsigned HOST_WIDE_INT cycles_used;
   unsigned HOST_WIDE_INT loop_count;
   
@@ -10930,6 +10940,9 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg,
 #undef  TARGET_CAN_ELIMINATE
 #define TARGET_CAN_ELIMINATE avr_can_eliminate
 
+#undef  TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
+#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS avr_allocate_stack_slots_for_args
+
 #undef  TARGET_CLASS_LIKELY_SPILLED_P
 #define TARGET_CLASS_LIKELY_SPILLED_P avr_class_likely_spilled_p
 
diff --git a/gcc/config/avr/avrlibc.h b/gcc/config/avr/avrlibc.h
new file mode 100644
index 00000000000..13fda0ff47e
--- /dev/null
+++ b/gcc/config/avr/avrlibc.h
@@ -0,0 +1,31 @@
+/* Definitions of target machine for the GNU compiler collection
+   for Atmel AVR micro controller.
+   Copyright (C) 2012
+   Free Software Foundation, Inc.
+   Contributed by Georg-Johann Lay (avr@gjlay.de)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+/* AVR-Libc implements functions from libgcc.a in libm.a, see PR54461.  */
+
+#undef  LIBGCC_SPEC
+#define LIBGCC_SPEC                                                     \
+  "%{!mmcu=at90s1*:%{!mmcu=attiny11:%{!mmcu=attiny12:%{!mmcu=attiny15:%{!mmcu=attiny28: -lgcc -lm }}}}}"
+
+#undef  LINK_GCC_C_SEQUENCE_SPEC
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "--start-group %G %L --end-group"
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index c231779b90b..5a19307a059 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -19,7 +19,7 @@
 
 ;;; Unused letters:
 ;;;     B     H           T  W
-;;;           h  k          v
+;;;           h jk          v
 
 ;; Integer register constraints.
 ;; It is not necessary to define 'r' here.
@@ -127,11 +127,6 @@
   (and (not (match_test "TARGET_X32"))
        (match_operand 0 "memory_operand")))
 
-(define_address_constraint "j"
-  "@internal Address operand that can be zero extended in LEA instruction."
-  (and (not (match_code "const_int"))
-       (match_operand 0 "address_operand")))
-
 ;; Integer constant constraints.
 (define_constraint "I"
   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index f300a56834d..14bc6729a98 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -92,8 +92,6 @@ extern void ix86_fixup_binary_operands_no_copy (enum rtx_code,
 extern void ix86_expand_binary_operator (enum rtx_code,
 					 enum machine_mode, rtx[]);
 extern bool ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);
-extern bool ix86_lea_outperforms (rtx, unsigned int, unsigned int,
-				  unsigned int, unsigned int);
 extern bool ix86_avoid_lea_for_add (rtx, rtx[]);
 extern bool ix86_use_lea_for_mov (rtx, rtx[]);
 extern bool ix86_avoid_lea_for_addr (rtx, rtx[]);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1701a2d1024..7d86bbb145c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11395,6 +11395,10 @@ ix86_address_subreg_operand (rtx op)
   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
     return false;
 
+  /* simplify_subreg does not handle stack pointer.  */
+  if (REGNO (op) == STACK_POINTER_REGNUM)
+    return false;
+
   /* Allow only SUBREGs of non-eliminable hard registers.  */
   return register_no_elim_operand (op, mode);
 }
@@ -11421,16 +11425,41 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
     {
       if (GET_CODE (addr) == ZERO_EXTEND
 	  && GET_MODE (XEXP (addr, 0)) == SImode)
-	addr = XEXP (addr, 0);
+	{
+	  addr = XEXP (addr, 0);
+	  if (CONST_INT_P (addr))
+	    return 0;
+	}	      
       else if (GET_CODE (addr) == AND
 	       && const_32bit_mask (XEXP (addr, 1), DImode))
 	{
 	  addr = XEXP (addr, 0);
 
-	  /* Strip subreg.  */
+	  /* Adjust SUBREGs.  */
 	  if (GET_CODE (addr) == SUBREG
 	      && GET_MODE (SUBREG_REG (addr)) == SImode)
-	    addr = SUBREG_REG (addr);
+	    {
+	      addr = SUBREG_REG (addr);
+	      if (CONST_INT_P (addr))
+		return 0;
+	    }
+	  else if (GET_MODE (addr) == DImode)
+	    addr = gen_rtx_SUBREG (SImode, addr, 0);
+	  else if (GET_MODE (addr) != VOIDmode)
+	    return 0;
+	}
+    }
+
+  /* Allow SImode subregs of DImode addresses,
+     they will be emitted with addr32 prefix.  */
+  if (TARGET_64BIT && GET_MODE (addr) == SImode)
+    {
+      if (GET_CODE (addr) == SUBREG
+	  && GET_MODE (SUBREG_REG (addr)) == DImode)
+	{
+	  addr = SUBREG_REG (addr);
+	  if (CONST_INT_P (addr))
+	    return 0;
 	}
     }
 
@@ -11541,6 +11570,19 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
       scale = 1 << scale;
       retval = -1;
     }
+  else if (CONST_INT_P (addr))
+    {
+      if (!x86_64_immediate_operand (addr, VOIDmode))
+	return 0;
+
+      /* Constant addresses are sign extended to 64bit, we have to
+	 prevent addresses from 0x80000000 to 0xffffffff in x32 mode.  */
+      if (TARGET_X32
+	  && val_signbit_known_set_p (SImode, INTVAL (addr)))
+	return 0;
+
+      disp = addr;
+    }
   else
     disp = addr;			/* displacement */
 
@@ -12044,13 +12086,6 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
   rtx base, index, disp;
   HOST_WIDE_INT scale;
 
-  /* Since constant address in x32 is signed extended to 64bit,
-     we have to prevent addresses from 0x80000000 to 0xffffffff.  */
-  if (TARGET_X32
-      && CONST_INT_P (addr)
-      && INTVAL (addr) < 0)
-    return false;
-
   if (ix86_decompose_address (addr, &parts) <= 0)
     /* Decomposition failed.  */
     return false;
@@ -13808,6 +13843,7 @@ get_some_local_dynamic_name (void)
    Z -- likewise, with special suffixes for x87 instructions.
    * -- print a star (in certain assembler syntax)
    A -- print an absolute memory reference.
+   E -- print address with DImode register names if TARGET_64BIT.
    w -- print the operand as if it's a "word" (HImode) even if it isn't.
    s -- print a shift double count, followed by the assemblers argument
 	delimiter.
@@ -13883,7 +13919,14 @@ ix86_print_operand (FILE *file, rtx x, int code)
 	  ix86_print_operand (file, x, 0);
 	  return;
 
+	case 'E':
+	  /* Wrap address in an UNSPEC to declare special handling.  */
+	  if (TARGET_64BIT)
+	    x = gen_rtx_UNSPEC (DImode, gen_rtvec (1, x), UNSPEC_LEA_ADDR);
 
+	  output_address (x);
+	  return;
+	    
 	case 'L':
 	  if (ASSEMBLER_DIALECT == ASM_ATT)
 	    putc ('l', file);
@@ -14488,6 +14531,7 @@ ix86_print_operand_address (FILE *file, rtx addr)
   int scale;
   int ok;
   bool vsib = false;
+  int code = 0;
 
   if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_VSIBADDR)
     {
@@ -14498,6 +14542,12 @@ ix86_print_operand_address (FILE *file, rtx addr)
       addr = XVECEXP (addr, 0, 0);
       vsib = true;
     }
+  else if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_LEA_ADDR)
+    {
+      gcc_assert (TARGET_64BIT);
+      ok = ix86_decompose_address (XVECEXP (addr, 0, 0), &parts);
+      code = 'q';
+    }
   else
     ok = ix86_decompose_address (addr, &parts);
 
@@ -14508,6 +14558,7 @@ ix86_print_operand_address (FILE *file, rtx addr)
       rtx tmp = SUBREG_REG (parts.base);
       parts.base = simplify_subreg (GET_MODE (parts.base),
 				    tmp, GET_MODE (tmp), 0);
+      gcc_assert (parts.base != NULL_RTX);
     }
 
   if (parts.index && GET_CODE (parts.index) == SUBREG)
@@ -14515,6 +14566,7 @@ ix86_print_operand_address (FILE *file, rtx addr)
       rtx tmp = SUBREG_REG (parts.index);
       parts.index = simplify_subreg (GET_MODE (parts.index),
 				     tmp, GET_MODE (tmp), 0);
+      gcc_assert (parts.index != NULL_RTX);
     }
 
   base = parts.base;
@@ -14568,15 +14620,23 @@ ix86_print_operand_address (FILE *file, rtx addr)
     }
   else
     {
-      int code = 0;
-
-      /* Print SImode registers for zero-extended addresses to force
-	 addr32 prefix.  Otherwise print DImode registers to avoid it.  */
-      if (TARGET_64BIT)
-	code = ((GET_CODE (addr) == ZERO_EXTEND
-		 || GET_CODE (addr) == AND)
-		? 'l'
-		: 'q');
+      /* Print SImode register names to force addr32 prefix.  */
+      if (GET_CODE (addr) == SUBREG)
+	{
+	  gcc_assert (TARGET_64BIT);
+	  gcc_assert (GET_MODE (addr) == SImode);
+	  gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode);
+	  gcc_assert (!code);
+	  code = 'l';
+	}
+      else if (GET_CODE (addr) == ZERO_EXTEND
+	       || GET_CODE (addr) == AND)
+	{
+	  gcc_assert (TARGET_64BIT);
+	  gcc_assert (GET_MODE (addr) == DImode);
+	  gcc_assert (!code);
+	  code = 'l';
+	}
 
       if (ASSEMBLER_DIALECT == ASM_ATT)
 	{
@@ -16650,9 +16710,9 @@ distance_agu_use (unsigned int regno0, rtx insn)
    over a sequence of instructions.  Instructions sequence has
    SPLIT_COST cycles higher latency than lea latency.  */
 
-bool
+static bool
 ix86_lea_outperforms (rtx insn, unsigned int regno0, unsigned int regno1,
-		      unsigned int regno2, unsigned int split_cost)
+		      unsigned int regno2, int split_cost)
 {
   int dist_define, dist_use;
 
@@ -16765,7 +16825,7 @@ ix86_use_lea_for_mov (rtx insn, rtx operands[])
   regno0 = true_regnum (operands[0]);
   regno1 = true_regnum (operands[1]);
 
-  return ix86_lea_outperforms (insn, regno0, regno1, -1, 0);
+  return ix86_lea_outperforms (insn, regno0, regno1, INVALID_REGNUM, 0);
 }
 
 /* Return true if we need to split lea into a sequence of
@@ -16775,12 +16835,17 @@ bool
 ix86_avoid_lea_for_addr (rtx insn, rtx operands[])
 {
   unsigned int regno0 = true_regnum (operands[0]) ;
-  unsigned int regno1 = -1;
-  unsigned int regno2 = -1;
-  unsigned int split_cost = 0;
+  unsigned int regno1 = INVALID_REGNUM;
+  unsigned int regno2 = INVALID_REGNUM;
+  int split_cost = 0;
   struct ix86_address parts;
   int ok;
 
+  /* FIXME: Handle zero-extended addresses.  */
+  if (GET_CODE (operands[1]) == ZERO_EXTEND
+      || GET_CODE (operands[1]) == AND)
+    return false;
+
   /* Check we need to optimize.  */
   if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
     return false;
@@ -16792,6 +16857,11 @@ ix86_avoid_lea_for_addr (rtx insn, rtx operands[])
   ok = ix86_decompose_address (operands[1], &parts);
   gcc_assert (ok);
 
+  /* There should be at least two components in the address.  */
+  if ((parts.base != NULL_RTX) + (parts.index != NULL_RTX)
+      + (parts.disp != NULL_RTX) + (parts.scale > 1) < 2)
+    return false;
+
   /* We should not split into add if non legitimate pic
      operand is used as displacement. */
   if (parts.disp && flag_pic && !LEGITIMATE_PIC_OPERAND_P (parts.disp))
@@ -23772,6 +23842,7 @@ ia32_multipass_dfa_lookahead (void)
     case PROCESSOR_CORE2_64:
     case PROCESSOR_COREI7_32:
     case PROCESSOR_COREI7_64:
+    case PROCESSOR_ATOM:
       /* Generally, we want haifa-sched:max_issue() to look ahead as far
 	 as many instructions can be executed on a cycle, i.e.,
 	 issue_rate.  I wonder why tuning for many CPUs does not do this.  */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 37cea7939ae..900a687fcb5 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -38,6 +38,7 @@
 ;; Z -- likewise, with special suffixes for x87 instructions.
 ;; * -- print a star (in certain assembler syntax)
 ;; A -- print an absolute memory reference.
+;; E -- print address with DImode register names if TARGET_64BIT.
 ;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
 ;; s -- print a shift double count, followed by the assemblers argument
 ;;	delimiter.
@@ -107,6 +108,7 @@
   UNSPEC_MS_TO_SYSV_CALL
   UNSPEC_CALL_NEEDS_VZEROUPPER
   UNSPEC_PAUSE
+  UNSPEC_LEA_ADDR
 
   ;; For SSE/MMX support:
   UNSPEC_FIX_NOTRUNC
@@ -626,7 +628,8 @@
 (define_attr "movu" "0,1" (const_string "0"))
 
 ;; Used to control the "enabled" attribute on a per-instruction basis.
-(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,bmi2"
+(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,
+		    bmi2,fma,fma4"
   (const_string "base"))
 
 (define_attr "enabled" ""
@@ -640,6 +643,9 @@
 	 (eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
 	 (eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
 	 (eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
+	 (eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
+	 (eq_attr "isa" "fma4")
+	   (symbol_ref "TARGET_FMA4 && !TARGET_FMA")
 	]
 	(const_int 1)))
 
@@ -1956,7 +1962,7 @@
       return "#";
 
     case TYPE_LEA:
-      return "lea{q}\t{%a1, %0|%0, %a1}";
+      return "lea{q}\t{%E1, %0|%0, %E1}";
 
     default:
       gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
@@ -1965,7 +1971,7 @@
       else if (which_alternative == 2)
 	return "movabs{q}\t{%1, %0|%0, %1}";
       else if (ix86_use_lea_for_mov (insn, operands))
-	return "lea{q}\t{%a1, %0|%0, %a1}";
+	return "lea{q}\t{%E1, %0|%0, %E1}";
       else
 	return "mov{q}\t{%1, %0|%0, %1}";
     }
@@ -2197,12 +2203,12 @@
       return "movd\t{%1, %0|%0, %1}";
 
     case TYPE_LEA:
-      return "lea{l}\t{%a1, %0|%0, %a1}";
+      return "lea{l}\t{%E1, %0|%0, %E1}";
 
     default:
       gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
       if (ix86_use_lea_for_mov (insn, operands))
-	return "lea{l}\t{%a1, %0|%0, %a1}";
+	return "lea{l}\t{%E1, %0|%0, %E1}";
       else
 	return "mov{l}\t{%1, %0|%0, %1}";
     }
@@ -2598,7 +2604,11 @@
 			     (const_int 8))
 	(match_operand:SWI48x 1 "nonmemory_operand" "Qn"))]
   "TARGET_64BIT"
-  "mov{b}\t{%b1, %h0|%h0, %b1}"
+{
+  if (CONST_INT_P (operands[1]))
+    operands[1] = simplify_gen_subreg (QImode, operands[1], <MODE>mode, 0);
+  return "mov{b}\t{%b1, %h0|%h0, %b1}";
+}
   [(set_attr "type" "imov")
    (set_attr "mode" "QI")])
 
@@ -2608,7 +2618,11 @@
 			 (const_int 8))
 	(match_operand:SI 1 "general_operand" "Qmn"))]
   "!TARGET_64BIT"
-  "mov{b}\t{%b1, %h0|%h0, %b1}"
+{
+  if (CONST_INT_P (operands[1]))
+    operands[1] = simplify_gen_subreg (QImode, operands[1], SImode, 0);
+  return "mov{b}\t{%b1, %h0|%h0, %b1}";
+}
   [(set_attr "type" "imov")
    (set_attr "mode" "QI")])
 
@@ -5373,6 +5387,41 @@
   DONE;
 })
 
+;; Load effective address instructions
+
+(define_insn_and_split "*lea<mode>"
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+	(match_operand:SWI48 1 "lea_address_operand" "p"))]
+  ""
+{
+  rtx addr = operands[1];
+
+  if (GET_CODE (addr) == SUBREG)
+    {
+      gcc_assert (TARGET_64BIT);
+      gcc_assert (<MODE>mode == SImode);
+      gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode);
+      return "lea{l}\t{%E1, %0|%0, %E1}";
+    }
+  else if (GET_CODE (addr) == ZERO_EXTEND
+	   || GET_CODE (addr) == AND)
+    {
+      gcc_assert (TARGET_64BIT);
+      gcc_assert (<MODE>mode == DImode);
+      return "lea{l}\t{%E1, %k0|%k0, %E1}";
+    }
+  else 
+    return "lea{<imodesuffix>}\t{%E1, %0|%0, %E1}";
+}
+  "reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
+  [(const_int 0)]
+{
+  ix86_split_lea_for_addr (operands, <MODE>mode);
+  DONE;
+}
+  [(set_attr "type" "lea")
+   (set_attr "mode" "<MODE>")])
+
 ;; Add instructions
 
 (define_expand "add<mode>3"
@@ -5431,72 +5480,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
-(define_insn_and_split "*lea_1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(subreg:SI (match_operand:DI 1 "lea_address_operand" "p") 0))]
-  "TARGET_64BIT"
-  "lea{l}\t{%a1, %0|%0, %a1}"
-  "&& reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
-  [(const_int 0)]
-{
-  ix86_split_lea_for_addr (operands, SImode);
-  DONE;
-}
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea<mode>_2"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-	(match_operand:SWI48 1 "lea_address_operand" "p"))]
-  ""
-  "lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
-  "reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
-  [(const_int 0)]
-{
-  ix86_split_lea_for_addr (operands, <MODE>mode);
-  DONE;
-}
-  [(set_attr "type" "lea")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*lea_3_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI
-	  (subreg:SI (match_operand:DI 1 "lea_address_operand" "j") 0)))]
-  "TARGET_64BIT"
-  "lea{l}\t{%a1, %k0|%k0, %a1}"
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
-(define_insn "*lea_4_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI
-	  (match_operand:SI 1 "lea_address_operand" "j")))]
-  "TARGET_64BIT"
-  "lea{l}\t{%a1, %k0|%k0, %a1}"
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
-(define_insn "*lea_5_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI
-	  (subreg:DI (match_operand:SI 1 "lea_address_operand" "p") 0)
-	  (match_operand:DI 2 "const_32bit_mask" "n")))]
-  "TARGET_64BIT"
-  "lea{l}\t{%a1, %k0|%k0, %a1}"
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
-(define_insn "*lea_6_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI
-	  (match_operand:DI 1 "lea_address_operand" "p")
-	  (match_operand:DI 2 "const_32bit_mask" "n")))]
-  "TARGET_64BIT"
-  "lea{l}\t{%a1, %k0|%k0, %a1}"
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
 (define_insn "*add<mode>_1"
   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
 	(plus:SWI48
@@ -12597,7 +12580,7 @@
   "!TARGET_64BIT && TARGET_GNU_TLS"
 {
   output_asm_insn
-    ("lea{l}\t{%a2@tlsgd(,%1,1), %0|%0, %a2@tlsgd[%1*1]}", operands);
+    ("lea{l}\t{%E2@tlsgd(,%1,1), %0|%0, %E2@tlsgd[%1*1]}", operands);
   if (TARGET_SUN_TLS)
 #ifdef HAVE_AS_IX86_TLSGDPLT
     return "call\t%a2@tlsgdplt";
@@ -12632,7 +12615,7 @@
   if (!TARGET_X32)
     fputs (ASM_BYTE "0x66\n", asm_out_file);
   output_asm_insn
-    ("lea{q}\t{%a1@tlsgd(%%rip), %%rdi|rdi, %a1@tlsgd[rip]}", operands);
+    ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands);
   fputs (ASM_SHORT "0x6666\n", asm_out_file);
   fputs ("\trex64\n", asm_out_file);
   if (TARGET_SUN_TLS)
@@ -12858,7 +12841,7 @@
 		  (unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")]
 			      UNSPEC_TLSDESC))))]
   "!TARGET_64BIT && TARGET_GNU2_TLS"
-  "lea{l}\t{%a2@TLSDESC(%1), %0|%0, %a2@TLSDESC[%1]}"
+  "lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}"
   [(set_attr "type" "lea")
    (set_attr "mode" "SI")
    (set_attr "length" "6")
@@ -12920,7 +12903,7 @@
 	(unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
 		   UNSPEC_TLSDESC))]
   "TARGET_64BIT && TARGET_GNU2_TLS"
-  "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}"
+  "lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}"
   [(set_attr "type" "lea")
    (set_attr "mode" "DI")
    (set_attr "length" "7")
@@ -16675,7 +16658,7 @@
 
     default:
       operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
-      return "lea{<imodesuffix>}\t{%a2, %0|%0, %a2}";
+      return "lea{<imodesuffix>}\t{%E2, %0|%0, %E2}";
     }
 }
   [(set (attr "type")
@@ -17734,7 +17717,7 @@
 (define_expand "stack_protect_set"
   [(match_operand 0 "memory_operand" "")
    (match_operand 1 "memory_operand" "")]
-  ""
+  "!TARGET_HAS_BIONIC"
 {
   rtx (*insn)(rtx, rtx);
 
@@ -17759,7 +17742,7 @@
 		    UNSPEC_SP_SET))
    (set (match_scratch:PTR 2 "=&r") (const_int 0))
    (clobber (reg:CC FLAGS_REG))]
-  ""
+  "!TARGET_HAS_BIONIC"
   "mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
   [(set_attr "type" "multi")])
 
@@ -17777,7 +17760,7 @@
   [(match_operand 0 "memory_operand" "")
    (match_operand 1 "memory_operand" "")
    (match_operand 2 "" "")]
-  ""
+  "!TARGET_HAS_BIONIC"
 {
   rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
 
@@ -17807,7 +17790,7 @@
 		     (match_operand:PTR 2 "memory_operand" "m")]
 		    UNSPEC_SP_TEST))
    (clobber (match_scratch:PTR 3 "=&r"))]
-  ""
+  "!TARGET_HAS_BIONIC"
   "mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
   [(set_attr "type" "multi")])
 
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 32f73dacdd8..c78384b300e 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -817,11 +817,6 @@
   struct ix86_address parts;
   int ok;
 
-  /*  LEA handles zero-extend by itself.  */
-  if (GET_CODE (op) == ZERO_EXTEND
-      || GET_CODE (op) == AND)
-    return false;
-
   ok = ix86_decompose_address (op, &parts);
   gcc_assert (ok);
   return parts.seg == SEG_DEFAULT;
@@ -963,6 +958,9 @@
   struct ix86_address parts;
   int ok;
 
+  if (TARGET_64BIT || !flag_pic)
+    return true;
+
   ok = ix86_decompose_address (XEXP (op, 0), &parts);
   gcc_assert (ok);
 
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 67d69bb5caf..b8d9bf242b3 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -395,8 +395,6 @@
 ;; Mix-n-match
 (define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
 
-(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
-
 ;; Mapping of immediate bits for blend instructions
 (define_mode_attr blendbits
   [(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
@@ -1687,28 +1685,12 @@
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
-;; FMA4 floating point multiply/accumulate instructions.  This
-;; includes the scalar version of the instructions as well as the
-;; vector.
+;; FMA floating point multiply/accumulate instructions.  These include
+;; scalar versions of the instructions as well as vector versions.
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-;; In order to match (*a * *b) + *c, particularly when vectorizing, allow
-;; combine to generate a multiply/add with two memory references.  We then
-;; split this insn, into loading up the destination register with one of the
-;; memory operations.  If we don't manage to split the insn, reload will
-;; generate the appropriate moves.  The reason this is needed, is that combine
-;; has already folded one of the memory references into both the multiply and
-;; add insns, and it can't generate a new pseudo.  I.e.:
-;;	(set (reg1) (mem (addr1)))
-;;	(set (reg2) (mult (reg1) (mem (addr2))))
-;;	(set (reg3) (plus (reg2) (mem (addr3))))
-;;
-;; ??? This is historic, pre-dating the gimple fma transformation.
-;; We could now properly represent that only one memory operand is
-;; allowed and not be penalized during optimization.
-
-;; Intrinsic FMA operations.
+(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
 
 ;; The standard names for fma is only available with SSE math enabled.
 (define_expand "fma<mode>4"
@@ -1743,7 +1725,7 @@
 	  (neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
   "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
 
-;; The builtin for fma4intrin.h is not constrained by SSE math enabled.
+;; The builtin for intrinsics is not constrained by SSE math enabled.
 (define_expand "fma4i_fmadd_<mode>"
   [(set (match_operand:FMAMODE 0 "register_operand")
 	(fma:FMAMODE
@@ -1752,70 +1734,137 @@
 	  (match_operand:FMAMODE 3 "nonimmediate_operand")))]
   "TARGET_FMA || TARGET_FMA4")
 
-(define_insn "*fma4i_fmadd_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
+(define_insn "*fma_fmadd_<mode>"
+  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
 	(fma:FMAMODE
-	  (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x")
-	  (match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
-	  (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4"
-  "vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemuladd")
+	  (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x")
+	  (match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
+	  (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x")))]
+  "TARGET_FMA || TARGET_FMA4"
+  "@
+   vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
+   vfmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+   vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma,fma4,fma4")
+   (set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*fma4i_fmsub_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
+(define_insn "*fma_fmsub_<mode>"
+  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
 	(fma:FMAMODE
-	  (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x")
-	  (match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
+	  (match_operand:FMAMODE   1 "nonimmediate_operand" "%0, 0,x, x,x")
+	  (match_operand:FMAMODE   2 "nonimmediate_operand" "xm, x,xm,x,m")
 	  (neg:FMAMODE
-	    (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x"))))]
-  "TARGET_FMA4"
-  "vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemuladd")
+	    (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x"))))]
+  "TARGET_FMA || TARGET_FMA4"
+  "@
+   vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
+   vfmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+   vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma,fma4,fma4")
+   (set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*fma4i_fnmadd_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
+(define_insn "*fma_fnmadd_<mode>"
+  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
 	(fma:FMAMODE
 	  (neg:FMAMODE
-	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x"))
-	  (match_operand:FMAMODE   2 "nonimmediate_operand" " x,m")
-	  (match_operand:FMAMODE   3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4"
-  "vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemuladd")
+	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x"))
+	  (match_operand:FMAMODE   2 "nonimmediate_operand" "xm, x,xm,x,m")
+	  (match_operand:FMAMODE   3 "nonimmediate_operand" " x,xm,0,xm,x")))]
+  "TARGET_FMA || TARGET_FMA4"
+  "@
+   vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
+   vfnmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+   vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma,fma4,fma4")
+   (set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*fma4i_fnmsub_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
+(define_insn "*fma_fnmsub_<mode>"
+  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
 	(fma:FMAMODE
 	  (neg:FMAMODE
-	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x"))
-	  (match_operand:FMAMODE   2 "nonimmediate_operand" " x,m")
+	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x"))
+	  (match_operand:FMAMODE   2 "nonimmediate_operand" "xm, x,xm,x,m")
 	  (neg:FMAMODE
-	    (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x"))))]
-  "TARGET_FMA4"
-  "vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemuladd")
+	    (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x"))))]
+  "TARGET_FMA || TARGET_FMA4"
+  "@
+   vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
+   vfnmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+   vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma,fma4,fma4")
+   (set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
 
-;; Scalar versions of the above.  Unlike ADDSS et al, these write the
-;; entire destination register, with the high-order elements zeroed.
+;; FMA parallel floating point multiply addsub and subadd operations.
 
-(define_expand "fma4i_vmfmadd_<mode>"
-  [(set (match_operand:VF_128 0 "register_operand")
-	(vec_merge:VF_128
-	  (fma:VF_128
-	    (match_operand:VF_128 1 "nonimmediate_operand")
-	    (match_operand:VF_128 2 "nonimmediate_operand")
-	    (match_operand:VF_128 3 "nonimmediate_operand"))
-	  (match_dup 4)
-	  (const_int 1)))]
-  "TARGET_FMA4"
-{
-  operands[4] = CONST0_RTX (<MODE>mode);
-})
+;; It would be possible to represent these without the UNSPEC as
+;;
+;; (vec_merge
+;;   (fma op1 op2 op3)
+;;   (fma op1 op2 (neg op3))
+;;   (merge-const))
+;;
+;; But this doesn't seem useful in practice.
+
+(define_expand "fmaddsub_<mode>"
+  [(set (match_operand:VF 0 "register_operand")
+	(unspec:VF
+	  [(match_operand:VF 1 "nonimmediate_operand")
+	   (match_operand:VF 2 "nonimmediate_operand")
+	   (match_operand:VF 3 "nonimmediate_operand")]
+	  UNSPEC_FMADDSUB))]
+  "TARGET_FMA || TARGET_FMA4")
+
+(define_insn "*fma_fmaddsub_<mode>"
+  [(set (match_operand:VF 0 "register_operand" "=x,x,x,x,x")
+	(unspec:VF
+	  [(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x, x,x")
+	   (match_operand:VF 2 "nonimmediate_operand" "xm, x,xm,x,m")
+	   (match_operand:VF 3 "nonimmediate_operand" " x,xm,0,xm,x")]
+	  UNSPEC_FMADDSUB))]
+  "TARGET_FMA || TARGET_FMA4"
+  "@
+   vfmaddsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
+   vfmaddsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vfmaddsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+   vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma,fma4,fma4")
+   (set_attr "type" "ssemuladd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*fma_fmsubadd_<mode>"
+  [(set (match_operand:VF 0 "register_operand" "=x,x,x,x,x")
+	(unspec:VF
+	  [(match_operand:VF   1 "nonimmediate_operand" "%0, 0,x, x,x")
+	   (match_operand:VF   2 "nonimmediate_operand" "xm, x,xm,x,m")
+	   (neg:VF
+	     (match_operand:VF 3 "nonimmediate_operand" " x,xm,0,xm,x"))]
+	  UNSPEC_FMADDSUB))]
+  "TARGET_FMA || TARGET_FMA4"
+  "@
+   vfmsubadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
+   vfmsubadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vfmsubadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+   vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma,fma4,fma4")
+   (set_attr "type" "ssemuladd")
+   (set_attr "mode" "<MODE>")])
+
+;; FMA3 floating point scalar intrinsics. These merge result with
+;; high-order elements from the destination register.
 
 (define_expand "fmai_vmfmadd_<mode>"
   [(set (match_operand:VF_128 0 "register_operand")
@@ -1900,6 +1949,23 @@
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
 
+;; FMA4 floating point scalar intrinsics.  These write the
+;; entire destination register, with the high-order elements zeroed.
+
+(define_expand "fma4i_vmfmadd_<mode>"
+  [(set (match_operand:VF_128 0 "register_operand")
+	(vec_merge:VF_128
+	  (fma:VF_128
+	    (match_operand:VF_128 1 "nonimmediate_operand")
+	    (match_operand:VF_128 2 "nonimmediate_operand")
+	    (match_operand:VF_128 3 "nonimmediate_operand"))
+	  (match_dup 4)
+	  (const_int 1)))]
+  "TARGET_FMA4"
+{
+  operands[4] = CONST0_RTX (<MODE>mode);
+})
+
 (define_insn "*fma4i_vmfmadd_<mode>"
   [(set (match_operand:VF_128 0 "register_operand" "=x,x")
 	(vec_merge:VF_128
@@ -1962,152 +2028,6 @@
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
-;; FMA4 Parallel floating point multiply addsub and subadd operations.
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; It would be possible to represent these without the UNSPEC as
-;;
-;; (vec_merge
-;;   (fma op1 op2 op3)
-;;   (fma op1 op2 (neg op3))
-;;   (merge-const))
-;;
-;; But this doesn't seem useful in practice.
-
-(define_expand "fmaddsub_<mode>"
-  [(set (match_operand:VF 0 "register_operand")
-	(unspec:VF
-	  [(match_operand:VF 1 "nonimmediate_operand")
-	   (match_operand:VF 2 "nonimmediate_operand")
-	   (match_operand:VF 3 "nonimmediate_operand")]
-	  UNSPEC_FMADDSUB))]
-  "TARGET_FMA || TARGET_FMA4")
-
-(define_insn "*fma4_fmaddsub_<mode>"
-  [(set (match_operand:VF 0 "register_operand" "=x,x")
-	(unspec:VF
-	  [(match_operand:VF 1 "nonimmediate_operand" "%x,x")
-	   (match_operand:VF 2 "nonimmediate_operand" " x,m")
-	   (match_operand:VF 3 "nonimmediate_operand" "xm,x")]
-	  UNSPEC_FMADDSUB))]
-  "TARGET_FMA4"
-  "vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*fma4_fmsubadd_<mode>"
-  [(set (match_operand:VF 0 "register_operand" "=x,x")
-	(unspec:VF
-	  [(match_operand:VF 1 "nonimmediate_operand" "%x,x")
-	   (match_operand:VF 2 "nonimmediate_operand" " x,m")
-	   (neg:VF
-	     (match_operand:VF 3 "nonimmediate_operand" "xm,x"))]
-	  UNSPEC_FMADDSUB))]
-  "TARGET_FMA4"
-  "vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; FMA3 floating point multiply/accumulate instructions.
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(define_insn "*fma_fmadd_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
-	(fma:FMAMODE
-	  (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x")
-	  (match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
-	  (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0")))]
-  "TARGET_FMA"
-  "@
-   vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
-   vfmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
-   vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*fma_fmsub_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
-	(fma:FMAMODE
-	  (match_operand:FMAMODE   1 "nonimmediate_operand" "%0, 0,x")
-	  (match_operand:FMAMODE   2 "nonimmediate_operand" "xm, x,xm")
-	  (neg:FMAMODE
-	    (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0"))))]
-  "TARGET_FMA"
-  "@
-   vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
-   vfmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
-   vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*fma_fnmadd_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
-	(fma:FMAMODE
-	  (neg:FMAMODE
-	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x"))
-	  (match_operand:FMAMODE   2 "nonimmediate_operand" "xm, x,xm")
-	  (match_operand:FMAMODE   3 "nonimmediate_operand" " x,xm,0")))]
-  "TARGET_FMA"
-  "@
-   vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
-   vfnmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
-   vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*fma_fnmsub_<mode>"
-  [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
-	(fma:FMAMODE
-	  (neg:FMAMODE
-	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x"))
-	  (match_operand:FMAMODE   2 "nonimmediate_operand" "xm, x,xm")
-	  (neg:FMAMODE
-	    (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0"))))]
-  "TARGET_FMA"
-  "@
-   vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
-   vfnmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
-   vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*fma_fmaddsub_<mode>"
-  [(set (match_operand:VF 0 "register_operand" "=x,x,x")
-	(unspec:VF
-	  [(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
-	   (match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
-	   (match_operand:VF 3 "nonimmediate_operand" " x,xm,0")]
-	  UNSPEC_FMADDSUB))]
-  "TARGET_FMA"
-  "@
-   vfmaddsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
-   vfmaddsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
-   vfmaddsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*fma_fmsubadd_<mode>"
-  [(set (match_operand:VF 0 "register_operand" "=x,x,x")
-	(unspec:VF
-	  [(match_operand:VF   1 "nonimmediate_operand" "%0, 0,x")
-	   (match_operand:VF   2 "nonimmediate_operand" "xm, x,xm")
-	   (neg:VF
-	     (match_operand:VF 3 "nonimmediate_operand" " x,xm,0"))]
-	  UNSPEC_FMADDSUB))]
-  "TARGET_FMA"
-  "@
-   vfmsubadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
-   vfmsubadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
-   vfmsubadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssemuladd")
-   (set_attr "mode" "<MODE>")])
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
 ;; Parallel single-precision floating point conversion operations
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -9619,7 +9539,7 @@
    (set_attr "mode" "TI")])
 
 (define_insn "<sse4_1_avx2>_pblendvb"
-  [(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand" "=x,x")
+  [(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
 	(unspec:VI1_AVX2
 	  [(match_operand:VI1_AVX2 1 "reg_not_xmm0_operand_maybe_avx"  "0,x")
 	   (match_operand:VI1_AVX2 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
@@ -10718,45 +10638,45 @@
 	    (vec_select:V2QI
 	     (match_operand:V16QI 1 "nonimmediate_operand" "xm")
 	     (parallel [(const_int 0)
-			(const_int 4)])))
+			(const_int 8)])))
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
 	     (parallel [(const_int 1)
-			(const_int 5)]))))
+			(const_int 9)]))))
 	  (plus:V2DI
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
 	     (parallel [(const_int 2)
-			(const_int 6)])))
+			(const_int 10)])))
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
 	     (parallel [(const_int 3)
-			(const_int 7)])))))
+			(const_int 11)])))))
 	 (plus:V2DI
 	  (plus:V2DI
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 8)
+	     (parallel [(const_int 4)
 			(const_int 12)])))
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 9)
+	     (parallel [(const_int 5)
 			(const_int 13)]))))
 	  (plus:V2DI
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 10)
+	     (parallel [(const_int 6)
 			(const_int 14)])))
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 11)
+	     (parallel [(const_int 7)
 			(const_int 15)])))))))]
   "TARGET_XOP"
   "vphaddbq\t{%1, %0|%0, %1}"
@@ -10904,45 +10824,45 @@
 	    (vec_select:V2QI
 	     (match_operand:V16QI 1 "nonimmediate_operand" "xm")
 	     (parallel [(const_int 0)
-			(const_int 4)])))
+			(const_int 8)])))
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
 	     (parallel [(const_int 1)
-			(const_int 5)]))))
+			(const_int 9)]))))
 	  (plus:V2DI
 	   (zero_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
 	     (parallel [(const_int 2)
-			(const_int 6)])))
+			(const_int 10)])))
 	   (zero_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
 	     (parallel [(const_int 3)
-			(const_int 7)])))))
+			(const_int 11)])))))
 	 (plus:V2DI
 	  (plus:V2DI
 	   (zero_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 8)
+	     (parallel [(const_int 4)
 			(const_int 12)])))
 	   (sign_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 9)
+	     (parallel [(const_int 5)
 			(const_int 13)]))))
 	  (plus:V2DI
 	   (zero_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 10)
+	     (parallel [(const_int 6)
 			(const_int 14)])))
 	   (zero_extend:V2DI
 	    (vec_select:V2QI
 	     (match_dup 1)
-	     (parallel [(const_int 11)
+	     (parallel [(const_int 7)
 			(const_int 15)])))))))]
   "TARGET_XOP"
   "vphaddubq\t{%1, %0|%0, %1}"
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 1ba43bb1e01..ddff1e680ea 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -28,10 +28,7 @@
 ])
 
 (define_c_enum "unspecv" [
-  UNSPECV_CMPXCHG_1
-  UNSPECV_CMPXCHG_2
-  UNSPECV_CMPXCHG_3
-  UNSPECV_CMPXCHG_4
+  UNSPECV_CMPXCHG
   UNSPECV_XCHG
   UNSPECV_LOCK
 ])
@@ -315,8 +312,9 @@
    (match_operand:SI 7 "const_int_operand" "")]		;; failure model
   "TARGET_CMPXCHG"
 {
-  emit_insn (gen_atomic_compare_and_swap_single<mode>
-	     (operands[1], operands[2], operands[3], operands[4]));
+  emit_insn
+   (gen_atomic_compare_and_swap<mode>_1
+    (operands[1], operands[2], operands[3], operands[4]));
   ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG),
 		     const0_rtx);
   DONE;
@@ -325,11 +323,7 @@
 (define_mode_iterator CASMODE
   [(DI "TARGET_64BIT || TARGET_CMPXCHG8B")
    (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
-(define_mode_iterator DCASMODE
-  [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
-   (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
-(define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
-(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
+(define_mode_attr CASHMODE [(DI "SI") (TI "DI")])
 
 (define_expand "atomic_compare_and_swap<mode>"
   [(match_operand:QI 0 "register_operand" "")		;; bool success output
@@ -344,12 +338,13 @@
 {
   if (<MODE>mode == DImode && TARGET_64BIT)
     {
-      emit_insn (gen_atomic_compare_and_swap_singledi
-		 (operands[1], operands[2], operands[3], operands[4]));
+      emit_insn
+       (gen_atomic_compare_and_swapdi_1
+	(operands[1], operands[2], operands[3], operands[4]));
     }
   else
     {
-      enum machine_mode hmode = <DCASHMODE>mode;
+      enum machine_mode hmode = <CASHMODE>mode;
       rtx lo_o, lo_e, lo_n, hi_o, hi_e, hi_n, mem;
 
       lo_o = operands[1];
@@ -363,31 +358,30 @@
       lo_e = gen_lowpart (hmode, lo_e);
       lo_n = gen_lowpart (hmode, lo_n);
 
-      if (<MODE>mode == DImode
-	  && !TARGET_64BIT
-	  && flag_pic
-	  && !cmpxchg8b_pic_memory_operand (mem, DImode))
-	mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
+      if (!cmpxchg8b_pic_memory_operand (mem, <MODE>mode))
+ 	mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
 
-      emit_insn (gen_atomic_compare_and_swap_double<mode>
-		 (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n));
+      emit_insn
+       (gen_atomic_compare_and_swap<mode>_doubleword
+        (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n));
     }
+
   ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG),
 		     const0_rtx);
   DONE;
 })
 
-(define_insn "atomic_compare_and_swap_single<mode>"
+(define_insn "atomic_compare_and_swap<mode>_1"
   [(set (match_operand:SWI 0 "register_operand" "=a")
 	(unspec_volatile:SWI
 	  [(match_operand:SWI 1 "memory_operand" "+m")
 	   (match_operand:SWI 2 "register_operand" "0")
 	   (match_operand:SWI 3 "register_operand" "<r>")]
-	  UNSPECV_CMPXCHG_1))
+	  UNSPECV_CMPXCHG))
    (set (match_dup 1)
-	(unspec_volatile:SWI [(const_int 0)] UNSPECV_CMPXCHG_2))
+	(unspec_volatile:SWI [(const_int 0)] UNSPECV_CMPXCHG))
    (set (reg:CCZ FLAGS_REG)
-        (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_3))]
+        (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))]
   "TARGET_CMPXCHG"
   "lock{%;} cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}")
 
@@ -396,50 +390,46 @@
 ;; not match the gcc register numbering, so the pair must be CX:BX.
 ;; That said, in order to take advantage of possible lower-subreg opts,
 ;; treat all of the integral operands in the same way.
-(define_insn "atomic_compare_and_swap_double<mode>"
-  [(set (match_operand:<DCASHMODE> 0 "register_operand" "=a")
-	(unspec_volatile:<DCASHMODE>
-	  [(match_operand:DCASMODE 2 "memory_operand" "+m")
-	   (match_operand:<DCASHMODE> 3 "register_operand" "0")
-	   (match_operand:<DCASHMODE> 4 "register_operand" "1")
-	   (match_operand:<DCASHMODE> 5 "register_operand" "b")
-	   (match_operand:<DCASHMODE> 6 "register_operand" "c")]
-	  UNSPECV_CMPXCHG_1))
-   (set (match_operand:<DCASHMODE> 1 "register_operand" "=d")
-	(unspec_volatile:<DCASHMODE> [(const_int 0)] UNSPECV_CMPXCHG_2))
-   (set (match_dup 2)
-	(unspec_volatile:DCASMODE [(const_int 0)] UNSPECV_CMPXCHG_3))
-   (set (reg:CCZ FLAGS_REG)
-        (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_4))]
-  ""
-  "lock{%;} cmpxchg<doublemodesuffix>b\t%2")
-
-;; Theoretically we'd like to use constraint "r" (any reg) for op5,
-;; but that includes ecx.  If op5 and op6 are the same (like when
-;; the input is -1LL) GCC might chose to allocate op5 to ecx, like
-;; op6.  This breaks, as the xchg will move the PIC register contents
-;; to %ecx then --> boom.  Operands 5 and 6 really need to be different
-;; registers, which in this case means op5 must not be ecx.  Instead
-;; of playing tricks with fake early clobbers or the like we just
-;; enumerate all regs possible here, which (as this is !TARGET_64BIT)
-;; are just esi and edi.
-(define_insn "*atomic_compare_and_swap_doubledi_pic"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(unspec_volatile:SI
-	  [(match_operand:DI 2 "cmpxchg8b_pic_memory_operand" "+m")
-	   (match_operand:SI 3 "register_operand" "0")
-	   (match_operand:SI 4 "register_operand" "1")
-	   (match_operand:SI 5 "register_operand" "SD")
-	   (match_operand:SI 6 "register_operand" "c")]
-	  UNSPECV_CMPXCHG_1))
-   (set (match_operand:SI 1 "register_operand" "=d")
-	(unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_2))
+
+;; Operands 5 and 6 really need to be different registers, which in
+;; this case means op5 must not be ecx.  If op5 and op6 are the same
+;; (like when the input is -1LL) GCC might chose to allocate op5 to ecx,
+;; like op6.  This breaks, as the xchg will move the PIC register
+;; contents to %ecx then --> boom.
+
+(define_mode_attr doublemodesuffix [(SI "8") (DI "16")])
+(define_mode_attr regprefix [(SI "e") (DI "r")])
+
+(define_insn "atomic_compare_and_swap<dwi>_doubleword"
+  [(set (match_operand:DWIH 0 "register_operand" "=a,a")
+	(unspec_volatile:DWIH
+	  [(match_operand:<DWI> 2 "cmpxchg8b_pic_memory_operand" "+m,m")
+	   (match_operand:DWIH 3 "register_operand" "0,0")
+	   (match_operand:DWIH 4 "register_operand" "1,1")
+	   (match_operand:DWIH 5 "register_operand" "b,!*r")
+	   (match_operand:DWIH 6 "register_operand" "c,c")]
+	  UNSPECV_CMPXCHG))
+   (set (match_operand:DWIH 1 "register_operand" "=d,d")
+	(unspec_volatile:DWIH [(const_int 0)] UNSPECV_CMPXCHG))
    (set (match_dup 2)
-	(unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG_3))
+	(unspec_volatile:<DWI> [(const_int 0)] UNSPECV_CMPXCHG))
    (set (reg:CCZ FLAGS_REG)
-        (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_4))]
-  "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
-  "xchg{l}\t%%ebx, %5\;lock{%;} cmpxchg8b\t%2\;xchg{l}\t%%ebx, %5")
+        (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))
+   (clobber (match_scratch:DWIH 7 "=X,&5"))]
+  "TARGET_CMPXCHG<doublemodesuffix>B"
+{
+  bool swap = REGNO (operands[5]) != BX_REG;
+
+  if (swap)
+    output_asm_insn ("xchg{<imodesuffix>}\t%%<regprefix>bx, %5", operands);
+
+  output_asm_insn ("lock{%;} cmpxchg<doublemodesuffix>b\t%2", operands);
+
+  if (swap)
+    output_asm_insn ("xchg{<imodesuffix>}\t%%<regprefix>bx, %5", operands);
+
+  return "";
+})
 
 ;; For operand 2 nonmemory_operand predicate is used instead of
 ;; register_operand to allow combiner to better optimize atomic
diff --git a/gcc/config/linux.h b/gcc/config/linux.h
index dbbeea5c7fd..fb459e68028 100644
--- a/gcc/config/linux.h
+++ b/gcc/config/linux.h
@@ -104,3 +104,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 /* Whether we have sincos that follows the GNU extension.  */
 #undef TARGET_HAS_SINCOS
 #define TARGET_HAS_SINCOS (OPTION_GLIBC || OPTION_BIONIC)
+
+/* Whether we have Bionic libc runtime */
+#undef TARGET_HAS_BIONIC
+#define TARGET_HAS_BIONIC (OPTION_BIONIC)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ae560d9aeba..02e757b5b4f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -15415,7 +15415,10 @@ mips_reorg (void)
     }
 
   if (optimize > 0 && flag_delayed_branch)
-    dbr_schedule (get_insns ());
+    {
+      cleanup_barriers ();
+      dbr_schedule (get_insns ());
+    }
   mips_reorg_process_insns ();
   if (!TARGET_MIPS16
       && TARGET_EXPLICIT_RELOCS
@@ -15584,6 +15587,9 @@ mips_set_mips16_mode (int mips16_p)
       /* Switch to MIPS16 mode.  */
       target_flags |= MASK_MIPS16;
 
+      /* Turn off SYNCI if it was on, MIPS16 doesn't support it.  */
+      target_flags &= ~MASK_SYNCI;
+
       /* Don't run the scheduler before reload, since it tends to
          increase register pressure.  */
       flag_schedule_insns = 0;
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index e1133cd9ba1..15f1adc3c1d 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -10663,7 +10663,10 @@ sparc_reorg (void)
   /* We need to have the (essentially) final form of the insn stream in order
      to properly detect the various hazards.  Run delay slot scheduling.  */
   if (optimize > 0 && flag_delayed_branch)
-    dbr_schedule (get_insns ());
+    {
+      cleanup_barriers ();
+      dbr_schedule (get_insns ());
+    }
 
   /* Now look for specific patterns in the insn stream.  */
   for (insn = get_insns (); insn; insn = next)
diff --git a/gcc/config/tilegx/feedback.h b/gcc/config/tilegx/feedback.h
new file mode 100644
index 00000000000..34e48ed8895
--- /dev/null
+++ b/gcc/config/tilegx/feedback.h
@@ -0,0 +1,14 @@
+#ifndef _FEEDBACK_H
+#define _FEEDBACK_H 1
+
+#ifdef __ASSEMBLER__
+
+/* Stub defines for feedback instrumentation.  */
+#define FEEDBACK_ENTER_EXPLICIT(FUNCNAME, SECNAME, SIZE)
+#define FEEDBACK_ENTER(FUNCNAME)
+#define FEEDBACK_REENTER(FUNCNAME)
+#define FEEDBACK_ENTRY(FUNCNAME, SECNAME, SIZE)
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _FEEDBACK_H */
diff --git a/gcc/config/tilegx/sync.md b/gcc/config/tilegx/sync.md
index e4d1e074f1a..9bf61d17dbe 100644
--- a/gcc/config/tilegx/sync.md
+++ b/gcc/config/tilegx/sync.md
@@ -72,7 +72,7 @@
          UNSPEC_CMPXCHG))]
   ""
   "cmpexch<four_if_si>\t%0, %1, %r2"
-  [(set_attr "type" "X1_L2")])
+  [(set_attr "type" "X1_remote")])
 
 
 (define_expand "atomic_exchange<mode>"
@@ -101,7 +101,7 @@
 	 UNSPEC_XCHG))]
   ""
   "exch<four_if_si>\t%0, %1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 
 (define_expand "atomic_fetch_<fetchop_name><mode>"
@@ -137,7 +137,7 @@
 	   UNSPEC_ATOMIC))]
   ""
   "fetch<fetchop_name><four_if_si>\t%0, %1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 
 (define_expand "atomic_fetch_sub<mode>"
diff --git a/gcc/config/tilegx/tilegx-generic.md b/gcc/config/tilegx/tilegx-generic.md
index 970344aacf4..7dea17ab078 100644
--- a/gcc/config/tilegx/tilegx-generic.md
+++ b/gcc/config/tilegx/tilegx-generic.md
@@ -51,6 +51,10 @@
   (eq_attr "type" "X1_L2")
   "X1")
 
+(define_insn_reservation "X1_remote" 50
+  (eq_attr "type" "X1_remote")
+  "X1")
+
 (define_insn_reservation "X1_miss" 80
   (eq_attr "type" "X1_miss")
   "X1")
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index 217682eaa66..424027ffae2 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -144,7 +144,7 @@ tilegx_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
 }
 
 
-/* TARGET_MODE_REP_EXTENDED.  */
+/* Implement TARGET_MODE_REP_EXTENDED.  */
 static int
 tilegx_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
 {
@@ -405,7 +405,7 @@ tilegx_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
 
   addr = create_tmp_var (ptr_type_node, "va_arg");
 
-  /* if an object is dynamically sized, a pointer to it is passed
+  /* If an object is dynamically sized, a pointer to it is passed
      instead of the object itself.  */
   pass_by_reference_p = pass_by_reference (NULL, TYPE_MODE (type), type,
 					   false);
@@ -457,11 +457,11 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
     {
     case CONST_INT:
       /* If this is an 8-bit constant, return zero since it can be
-         used nearly anywhere with no cost.  If it is a valid operand
-         for an ADD or AND, likewise return 0 if we know it will be
-         used in that context.  Otherwise, return 2 since it might be
-         used there later.  All other constants take at least two
-         insns.  */
+	 used nearly anywhere with no cost.  If it is a valid operand
+	 for an ADD or AND, likewise return 0 if we know it will be
+	 used in that context.  Otherwise, return 2 since it might be
+	 used there later.  All other constants take at least two
+	 insns.  */
       if (satisfies_constraint_I (x))
 	{
 	  *total = 0;
@@ -506,8 +506,8 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
 
     case MEM:
       /* If outer-code was a sign or zero extension, a cost of
-         COSTS_N_INSNS (1) was already added in, so account for
-         that.  */
+	 COSTS_N_INSNS (1) was already added in, so account for
+	 that.  */
       if (outer_code == ZERO_EXTEND || outer_code == SIGN_EXTEND)
 	*total = COSTS_N_INSNS (1);
       else
@@ -635,7 +635,7 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
 static rtx
 create_temp_reg_if_possible (enum machine_mode mode, rtx default_reg)
 {
-  return can_create_pseudo_p ()? gen_reg_rtx (mode) : default_reg;
+  return can_create_pseudo_p () ? gen_reg_rtx (mode) : default_reg;
 }
 
 
@@ -1335,8 +1335,8 @@ tilegx_simd_int (rtx num, enum machine_mode mode)
 
 
 /* Returns true iff VAL can be moved into a register in one
-   instruction.  And if it can, it emits the code to move the
-   constant into DEST_REG.
+   instruction.  And if it can, it emits the code to move the constant
+   into DEST_REG.
 
    If THREE_WIDE_ONLY is true, this insists on an instruction that
    works in a bundle containing three instructions.  */
@@ -1396,7 +1396,7 @@ tilegx_bitfield_operand_p (HOST_WIDE_INT n, int *first_bit, int *last_bit)
 	continue;
 
       /* See if x is a power of two minus one, i.e. only consecutive 1
-         bits starting from bit 0.  */
+	 bits starting from bit 0.  */
       if ((x & (x + 1)) == 0)
 	{
 	  if (first_bit != NULL)
@@ -1480,8 +1480,8 @@ expand_set_cint64 (rtx dest_reg, rtx src_val)
 	  if (expand_set_cint64_one_inst (temp, r, three_wide_only))
 	    {
 	      /* 0xFFFFFFFFFFA5FFFF becomes:
-	         movei temp, 0xFFFFFFFFFFFFFFA5
-	         rotli dest, temp, 16  */
+		 movei temp, 0xFFFFFFFFFFFFFFA5
+		 rotli dest, temp, 16  */
 	      emit_move_insn (dest_reg,
 			      gen_rtx_ROTATE (DImode, temp, GEN_INT (count)));
 	      return;
@@ -1530,11 +1530,11 @@ expand_set_cint64 (rtx dest_reg, rtx src_val)
       unsigned HOST_WIDE_INT leftover;
 
       /* Recursively create the constant above the lowest 16 zero
-         bits.  */
+	 bits.  */
       expand_set_cint64 (temp, GEN_INT (val >> shift));
 
       /* See if we can easily insert the remaining bits, or if we need
-         to fall through to the more general case.  */
+	 to fall through to the more general case.  */
       leftover = val - ((val >> shift) << shift);
       if (leftover == 0)
 	{
@@ -1571,8 +1571,8 @@ expand_set_cint64 (rtx dest_reg, rtx src_val)
   else
     {
       /* Set as many high 16-bit blocks as we can with a single
-         instruction.  We'll insert the remaining 16-bit blocks
-         below.  */
+	 instruction.  We'll insert the remaining 16-bit blocks
+	 below.  */
       for (shift = 16;; shift += 16)
 	{
 	  gcc_assert (shift < 64);
@@ -1615,10 +1615,10 @@ tilegx_expand_set_const64 (rtx op0, rtx op1)
   if (CONST_INT_P (op1))
     {
       /* TODO: I don't know if we want to split large constants
-         now, or wait until later (with a define_split).
+	 now, or wait until later (with a define_split).
 
-         Does splitting early help CSE?  Does it harm other
-         optimizations that might fold loads? */
+	 Does splitting early help CSE?  Does it harm other
+	 optimizations that might fold loads?  */
       expand_set_cint64 (op0, op1);
     }
   else
@@ -1716,7 +1716,7 @@ tilegx_expand_unaligned_load (rtx dest_reg, rtx mem, HOST_WIDE_INT bitsize,
   if (bitsize == 2 * BITS_PER_UNIT && (bit_offset % BITS_PER_UNIT) == 0)
     {
       /* When just loading a two byte value, we can load the two bytes
-         individually and combine them efficiently.  */
+	 individually and combine them efficiently.  */
 
       mem_lo = adjust_address (mem, QImode, byte_offset);
       mem_hi = adjust_address (mem, QImode, byte_offset + 1);
@@ -2053,6 +2053,7 @@ tilegx_expand_const_muldi (rtx op0, rtx op1, long long multiplier)
     return false;
 }
 
+
 /* Expand the muldi pattern.  */
 bool
 tilegx_expand_muldi (rtx op0, rtx op1, rtx op2)
@@ -2227,7 +2228,7 @@ tilegx_emit_setcc_internal (rtx res, enum rtx_code code, rtx op0, rtx op1,
     case GEU:
     case GTU:
       /* We do not have these compares, so we reverse the
-         operands.  */
+	 operands.  */
       swap = true;
       break;
 
@@ -2322,7 +2323,7 @@ tilegx_emit_cc_test (enum rtx_code code, rtx op0, rtx op1,
     case GEU:
     case GTU:
       /* These must be reversed (except NE, but let's
-         canonicalize).  */
+	 canonicalize).  */
       code = reverse_condition (code);
       branch_code = EQ;
       break;
@@ -2352,7 +2353,7 @@ tilegx_emit_cc_test (enum rtx_code code, rtx op0, rtx op1,
 		   || (REG_P (op0) && REG_POINTER (op0))))
 	    {
 	      /* TODO: Use a SIMD add immediate to hit zero for tiled
-	         constants in a single instruction.  */
+		 constants in a single instruction.  */
 	      if (GET_MODE (op0) != DImode)
 		{
 		  /* Convert to DImode so we can use addli.  Note that
@@ -3400,47 +3401,47 @@ tilegx_expand_builtin (tree exp,
 
   opnum = nonvoid;
   FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
-  {
-    const struct insn_operand_data *insn_op;
+    {
+      const struct insn_operand_data *insn_op;
 
-    if (arg == error_mark_node)
-      return NULL_RTX;
-    if (opnum > MAX_BUILTIN_ARGS)
-      return NULL_RTX;
+      if (arg == error_mark_node)
+	return NULL_RTX;
+      if (opnum > MAX_BUILTIN_ARGS)
+	return NULL_RTX;
 
-    insn_op = &insn_data[icode].operand[opnum];
+      insn_op = &insn_data[icode].operand[opnum];
 
-    op[opnum] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
+      op[opnum] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
 
-    if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
-      {
-	enum machine_mode opmode = insn_op->mode;
+      if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
+	{
+	  enum machine_mode opmode = insn_op->mode;
 
-	/* pointer_operand and pmode_register_operand operands do
-	   not specify a mode, so use the operand's mode instead
-	   (which should always be right by the time we get here,
-	   except for constants, which are VOIDmode).  */
-	if (opmode == VOIDmode)
-	  {
-	    enum machine_mode m = GET_MODE (op[opnum]);
-	    gcc_assert (m == Pmode || m == VOIDmode);
-	    opmode = Pmode;
-	  }
+	  /* pointer_operand and pmode_register_operand operands do
+	     not specify a mode, so use the operand's mode instead
+	     (which should always be right by the time we get here,
+	     except for constants, which are VOIDmode).  */
+	  if (opmode == VOIDmode)
+	    {
+	      enum machine_mode m = GET_MODE (op[opnum]);
+	      gcc_assert (m == Pmode || m == VOIDmode);
+	      opmode = Pmode;
+	    }
 
-	op[opnum] = copy_to_mode_reg (opmode, op[opnum]);
-      }
+	  op[opnum] = copy_to_mode_reg (opmode, op[opnum]);
+	}
 
-    if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
-      {
-	/* We still failed to meet the predicate even after moving
-	   into a register. Assume we needed an immediate.  */
-	error_at (EXPR_LOCATION (exp),
-		  "operand must be an immediate of the right size");
-	return const0_rtx;
-      }
+      if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
+	{
+	  /* We still failed to meet the predicate even after moving
+	     into a register. Assume we needed an immediate.  */
+	  error_at (EXPR_LOCATION (exp),
+		    "operand must be an immediate of the right size");
+	  return const0_rtx;
+	}
 
-    opnum++;
-  }
+      opnum++;
+    }
 
   if (nonvoid)
     {
@@ -3874,7 +3875,7 @@ tilegx_expand_prologue (void)
       REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
 
       /* fp holds a copy of the incoming sp, in case we need to store
-         it.  */
+	 it.  */
       sp_copy_regno = HARD_FRAME_POINTER_REGNUM;
     }
   else if (!tilegx_current_function_is_leaf ())
@@ -4069,7 +4070,7 @@ tilegx_expand_epilogue (bool sibcall_p)
   if (frame_pointer_needed)
     {
       /* Restore the old stack pointer by copying from the frame
-         pointer.  */
+	 pointer.  */
       if (TARGET_32BIT)
 	{
 	  insn = emit_insn (gen_sp_restore_32bit (stack_pointer_rtx,
@@ -4266,6 +4267,7 @@ get_jump_target (rtx branch)
   return 0;
 }
 
+
 /* Implement TARGET_SCHED_ADJUST_COST.  */
 static int
 tilegx_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
@@ -4311,37 +4313,37 @@ tilegx_gen_bundles (void)
 {
   basic_block bb;
   FOR_EACH_BB (bb)
-  {
-    rtx insn, next;
-    rtx end = NEXT_INSN (BB_END (bb));
+    {
+      rtx insn, next;
+      rtx end = NEXT_INSN (BB_END (bb));
 
-    for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
-      {
-	next = next_insn_to_bundle (NEXT_INSN (insn), end);
+      for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
+	{
+	  next = next_insn_to_bundle (NEXT_INSN (insn), end);
 
-	/* Never wrap {} around inline asm.  */
-	if (GET_CODE (PATTERN (insn)) != ASM_INPUT)
-	  {
-	    if (next == NULL_RTX || GET_MODE (next) == TImode
-		/* NOTE: The scheduler incorrectly believes a call
-		   insn can execute in the same cycle as the insn
-		   after the call.  This is of course impossible.
-		   Really we need to fix the scheduler somehow, so
-		   the code after the call gets scheduled
-		   optimally.  */
-		|| CALL_P (insn))
-	      {
-		/* Mark current insn as the end of a bundle.  */
-		PUT_MODE (insn, QImode);
-	      }
-	    else
-	      {
-		/* Mark it as part of a bundle.  */
-		PUT_MODE (insn, SImode);
-	      }
-	  }
-      }
-  }
+	  /* Never wrap {} around inline asm.  */
+	  if (GET_CODE (PATTERN (insn)) != ASM_INPUT)
+	    {
+	      if (next == NULL_RTX || GET_MODE (next) == TImode
+		  /* NOTE: The scheduler incorrectly believes a call
+		     insn can execute in the same cycle as the insn
+		     after the call.  This is of course impossible.
+		     Really we need to fix the scheduler somehow, so
+		     the code after the call gets scheduled
+		     optimally.  */
+		  || CALL_P (insn))
+		{
+		  /* Mark current insn as the end of a bundle.  */
+		  PUT_MODE (insn, QImode);
+		}
+	      else
+		{
+		  /* Mark it as part of a bundle.  */
+		  PUT_MODE (insn, SImode);
+		}
+	    }
+	}
+    }
 }
 
 
@@ -4906,7 +4908,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
   switch (code)
     {
     case 'c':
-      /* Print the compare operator opcode for conditional moves. */
+      /* Print the compare operator opcode for conditional moves.  */
       switch (GET_CODE (x))
 	{
 	case EQ:
@@ -4921,7 +4923,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'C':
-      /* Print the compare operator opcode for conditional moves. */
+      /* Print the compare operator opcode for conditional moves.  */
       switch (GET_CODE (x))
 	{
 	case EQ:
@@ -4937,7 +4939,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
 
     case 'd':
       {
-	/* Print the compare operator opcode for conditional moves. */
+	/* Print the compare operator opcode for conditional moves.  */
 	switch (GET_CODE (x))
 	  {
 	  case EQ:
@@ -4954,7 +4956,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
 
     case 'D':
       {
-	/* Print the compare operator opcode for conditional moves. */
+	/* Print the compare operator opcode for conditional moves.  */
 	switch (GET_CODE (x))
 	  {
 	  case EQ:
@@ -5196,7 +5198,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
 
     case 'r':
       /* In this case we need a register.  Use 'zero' if the operand
-         is const0_rtx.  */
+	 is const0_rtx.  */
       if (x == const0_rtx
 	  || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
 	{
@@ -5283,7 +5285,7 @@ tilegx_final_prescan_insn (rtx insn)
 }
 
 
-/* While emitting asm, are we currently inside '{' for a bundle? */
+/* While emitting asm, are we currently inside '{' for a bundle?  */
 static bool tilegx_in_bundle = false;
 
 /* Implement ASM_OUTPUT_OPCODE.  Prepend/append curly braces as
@@ -5336,7 +5338,7 @@ tilegx_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
       fprintf (file,
 	       "\t{\n"
 	       "\tmove\tr10, lr\n"
-	       "\tjal\t%s@plt\n"
+	       "\tjal\tplt(%s)\n"
 	       "\t}\n", MCOUNT_NAME);
     }
   else
@@ -5345,7 +5347,7 @@ tilegx_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
 	       "\t{\n"
 	       "\tmove\tr10, lr\n"
 	       "\tjal\t%s\n"
-	       "\t}\t\n", MCOUNT_NAME);
+	       "\t}\n", MCOUNT_NAME);
     }
 
   tilegx_in_bundle = false;
@@ -5458,7 +5460,7 @@ tilegx_file_end (void)
 #undef  TARGET_BUILTIN_DECL
 #define TARGET_BUILTIN_DECL tilegx_builtin_decl
 
-#undef   TARGET_EXPAND_BUILTIN
+#undef  TARGET_EXPAND_BUILTIN
 #define TARGET_EXPAND_BUILTIN tilegx_expand_builtin
 
 #undef  TARGET_CONDITIONAL_REGISTER_USAGE
diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 033d125a99b..048fe3a90c5 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -250,7 +250,7 @@
 
 ;; Define an insn type attribute.  This defines what pipes things can go in.
 (define_attr "type"
-  "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing"
+  "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_remote,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing"
   (const_string "Y01"))
 
 (define_attr "length" ""
@@ -408,7 +408,7 @@
 			(ss_minus "")
 			(us_minus "")
 			])
- 
+
 ;; <s> is the load/store extension suffix.
 (define_code_attr s [(zero_extend "u")
 		     (sign_extend "s")])
@@ -816,11 +816,11 @@
       bit_width = INTVAL (operands[2]);
       bit_offset = INTVAL (operands[3]);
 
-      /* Reject bitfields that can be done with a normal load */
+      /* Reject bitfields that can be done with a normal load.  */
       if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
         FAIL;
 
-      /* The value in memory cannot span more than 8 bytes. */
+      /* The value in memory cannot span more than 8 bytes.  */
       first_byte_offset = bit_offset / BITS_PER_UNIT;
       last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
       if (last_byte_offset - first_byte_offset > 7)
@@ -845,7 +845,6 @@
   HOST_WIDE_INT bit_width = INTVAL (operands[2]);
   HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
 
-
   if (MEM_P (operands[1]))
     {
       HOST_WIDE_INT first_byte_offset, last_byte_offset;
@@ -853,11 +852,11 @@
       if (GET_MODE (operands[1]) != QImode)
         FAIL;
 
-      /* Reject bitfields that can be done with a normal load */
+      /* Reject bitfields that can be done with a normal load.  */
       if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
         FAIL;
 
-      /* The value in memory cannot span more than 8 bytes. */
+      /* The value in memory cannot span more than 8 bytes.  */
       first_byte_offset = bit_offset / BITS_PER_UNIT;
       last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
       if (last_byte_offset - first_byte_offset > 7)
@@ -873,7 +872,7 @@
 
     if (bit_offset == 0)
       {
-	 /* Extracting the low bits is just a bitwise AND. */
+	 /* Extracting the low bits is just a bitwise AND.  */
 	 HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << bit_width) - 1;
 	 emit_insn (gen_anddi3 (operands[0], operands[1], GEN_INT (mask)));
 	 DONE;
@@ -891,7 +890,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(const:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
 			     UNSPEC_HW2_LAST)))])
-  
+
 ;; Second step of the 3-insn sequence to materialize a symbolic
 ;; address.
 (define_expand "mov_address_step2"
@@ -947,7 +946,7 @@
   "%1 = . + 8\n\tlnk\t%0"
   [(set_attr "type" "Y1")])
 
-;; First step of the 3-insn sequence to materialize a position
+;; The next three patterns are used to to materialize a position
 ;; independent address by adding the difference of two labels to a
 ;; base label in the text segment, assuming that the difference fits
 ;; in 32 signed bits.
@@ -959,10 +958,6 @@
                         UNSPEC_HW1_LAST_PCREL)))]
   "flag_pic")
   
-;; Second step of the 3-insn sequence to materialize a position
-;; independent address by adding the difference of two labels to a
-;; base label in the text segment, assuming that the difference fits
-;; in 32 signed bits.
 (define_expand "mov_pcrel_step2<bitsuffix>"
   [(set (match_operand:I48MODE 0 "register_operand" "")
 	(unspec:I48MODE
@@ -973,11 +968,7 @@
 			   UNSPEC_HW0_PCREL))]
 	 UNSPEC_INSN_ADDR_SHL16INSLI))]
   "flag_pic")
-  
-;; Third step of the 3-insn sequence to materialize a position
-;; independent address by adding the difference of two labels to a base
-;; label in the text segment, assuming that the difference fits in 32
-;; signed bits.
+
 (define_insn "mov_pcrel_step3<bitsuffix>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
         (unspec:I48MODE [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
@@ -1335,7 +1326,6 @@
   DONE;
 })
 
-
 (define_expand "subdf3"
   [(set (match_operand:DF 0 "register_operand" "")
         (minus:DF (match_operand:DF 1 "register_operand" "")
@@ -1708,7 +1698,6 @@
   "ctz\t%0, %r1"
   [(set_attr "type" "Y0")])
 
-
 (define_insn "popcount<mode>2"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
 	(popcount:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
@@ -1937,7 +1926,7 @@
 (define_insn "*zero_extendsidi_truncdisi"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
-	 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "0"))))]
+	 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))))]
   ""
   "v4int_l\t%0, zero, %r1"
   [(set_attr "type" "X01")])
@@ -2008,7 +1997,7 @@
   shruxi\t%0, %r1, %2
   shrux\t%0, %r1, %r2"
   [(set_attr "type" "X01,X01")])
-  
+
 (define_insn "*lshrsi_truncdisi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lshiftrt:SI
@@ -2213,7 +2202,8 @@
 ;; Loops
 ;;
 
-;; Define the subtract-one-and-jump insns so loop.c knows what to generate.
+;; Define the subtract-one-and-jump insns so loop.c knows what to
+;; generate.
 (define_expand "doloop_end"
   [(use (match_operand 0 "" ""))    ;; loop pseudo
    (use (match_operand 1 "" ""))    ;; iterations; zero if unknown
@@ -2481,8 +2471,8 @@
  [(set_attr "type" "*,*,X01")])
 
 ;; Used for move sp, r52, to pop a stack frame.  We need to make sure
-;; that stack frame memory operations have been issued before we do this.
-;; TODO: see above TODO.
+;; that stack frame memory operations have been issued before we do
+;; this.  TODO: see above TODO.
 (define_insn "sp_restore<bitsuffix>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
         (match_operand:I48MODE 1 "register_operand" "r"))
@@ -2627,7 +2617,7 @@
   "bfextu\t%0, %r1, %2, %3"
   [(set_attr "type" "X0")])
 
-(define_insn "*bfins"
+(define_insn "insn_bfins"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
                     (match_operand:DI 2 "reg_or_0_operand" "rO")
@@ -2638,36 +2628,6 @@
    "bfins\t%0, %r2, %3, %4"
    [(set_attr "type" "X0")])
 
-(define_expand "insn_bfins"
-  [(set (match_operand:DI 0 "register_operand" "")
-        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "")
-                    (match_operand:DI 2 "reg_or_0_operand" "")
-                    (match_operand:DI 3 "u6bit_cint_operand" "")
-                    (match_operand:DI 4 "u6bit_cint_operand" "")]
-                   UNSPEC_INSN_BFINS))]
-  "INTVAL (operands[3]) != 64"
-{
-  HOST_WIDE_INT first = INTVAL (operands[3]);
-  HOST_WIDE_INT last = INTVAL (operands[4]);
-
-  if (last >= first)
-    {
-      /* This is not a wacky wraparound case, so we can express this
-         as a standard insv. */
-      if (operands[0] != operands[1])
-        {
-	  operands[2] = make_safe_from (operands[2], operands[0]);
-	  emit_move_insn (operands[0], operands[1]);
-	}
-
-      emit_insn (gen_insv (operands[0],
-			   GEN_INT (last - first + 1), operands[3],
-			   operands[2]));
-
-      DONE;
-    }
-})
-
 (define_insn "insn_cmpexch<four_if_si>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
         (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
@@ -2679,7 +2639,7 @@
 	 UNSPEC_INSN_CMPEXCH))]
   ""
   "cmpexch<four_if_si>\t%0, %r1, %r2"
-  [(set_attr "type" "X1_L2")])
+  [(set_attr "type" "X1_remote")])
 
 (define_insn "insn_cmul"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2817,7 +2777,7 @@
 	 UNSPEC_INSN_EXCH))]
   ""
   "exch<four_if_si>\t%0, %r1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 (define_insn "insn_fdouble_add_flags"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2903,7 +2863,7 @@
                       (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
   ""
   "fetchadd<four_if_si>\t%0, %r1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 (define_insn "insn_fetchaddgez<four_if_si>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
@@ -2916,7 +2876,7 @@
                         UNSPEC_INSN_FETCHADDGEZ))]
   ""
   "fetchaddgez<four_if_si>\t%0, %r1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 (define_insn "insn_fetchand<four_if_si>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
@@ -2928,7 +2888,7 @@
                      (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
   ""
   "fetchand<four_if_si>\t%0, %r1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 (define_insn "insn_fetchor<four_if_si>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
@@ -2940,7 +2900,7 @@
                      (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
   ""
   "fetchor<four_if_si>\t%0, %r1, %r2"
-  [(set_attr "type" "X1_2cycle")])
+  [(set_attr "type" "X1_remote")])
 
 (define_insn "insn_finv"
   [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
diff --git a/gcc/config/tilepro/feedback.h b/gcc/config/tilepro/feedback.h
new file mode 100644
index 00000000000..34e48ed8895
--- /dev/null
+++ b/gcc/config/tilepro/feedback.h
@@ -0,0 +1,14 @@
+#ifndef _FEEDBACK_H
+#define _FEEDBACK_H 1
+
+#ifdef __ASSEMBLER__
+
+/* Stub defines for feedback instrumentation.  */
+#define FEEDBACK_ENTER_EXPLICIT(FUNCNAME, SECNAME, SIZE)
+#define FEEDBACK_ENTER(FUNCNAME)
+#define FEEDBACK_REENTER(FUNCNAME)
+#define FEEDBACK_ENTRY(FUNCNAME, SECNAME, SIZE)
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _FEEDBACK_H */
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 011ac083add..7cdb555a53e 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -4913,7 +4913,7 @@ tilepro_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
       fprintf (file,
 	       "\t{\n"
 	       "\tmove\tr10, lr\n"
-	       "\tjal\t%s@plt\n"
+	       "\tjal\tplt(%s)\n"
 	       "\t}\n", MCOUNT_NAME);
     }
   else
diff --git a/gcc/configure b/gcc/configure
index 2768934c0b9..aa011b29847 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -26723,6 +26723,11 @@ else
 	     $target_header_dir/bits/uClibc_config.h > /dev/null; then
 	  gcc_cv_libc_provides_ssp=yes
 	fi
+      # all versions of Bionic support stack protector
+      elif test -f $target_header_dir/sys/cdefs.h \
+        && $EGREP '^[  ]*#[    ]*define[       ]+__BIONIC__[   ]+1' \
+           $target_header_dir/sys/cdefs.h > /dev/null; then
+         gcc_cv_libc_provides_ssp=yes
       fi
 	;;
        *-*-gnu*)
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 804a3dd7100..8adf6b9dbb4 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -4633,6 +4633,11 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
 	     $target_header_dir/bits/uClibc_config.h > /dev/null; then
 	  gcc_cv_libc_provides_ssp=yes
 	fi
+      # all versions of Bionic support stack protector
+      elif test -f $target_header_dir/sys/cdefs.h \
+        && $EGREP '^[  ]*#[    ]*define[       ]+__BIONIC__[   ]+1' \
+           $target_header_dir/sys/cdefs.h > /dev/null; then
+         gcc_cv_libc_provides_ssp=yes
       fi]
 	;;
        *-*-gnu*)
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index ba3d4828255..458a276e8ad 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,8 @@
+2012-08-31  Ollie Wild  <aaw@google.com>
+
+	PR c++/54197
+	* call.c (extend_ref_init_temps_1): Handle COMPOUND_EXPR trees.
+
 2012-07-20  Jason Merrill  <jason@redhat.com>
 
 	PR c++/54038
diff --git a/gcc/cp/call.c b/gcc/cp/call.c
index 5e74f56e55f..648d0032acc 100644
--- a/gcc/cp/call.c
+++ b/gcc/cp/call.c
@@ -8773,6 +8773,12 @@ extend_ref_init_temps_1 (tree decl, tree init, VEC(tree,gc) **cleanups)
   tree sub = init;
   tree *p;
   STRIP_NOPS (sub);
+  if (TREE_CODE (sub) == COMPOUND_EXPR)
+    {
+      TREE_OPERAND (sub, 1)
+        = extend_ref_init_temps_1 (decl, TREE_OPERAND (sub, 1), cleanups);
+      return init;
+    }
   if (TREE_CODE (sub) != ADDR_EXPR)
     return init;
   /* Deal with binding to a subobject.  */
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 0e9e2b497ba..3f2c27def20 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1063,6 +1063,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_HAS_SINCOS 0
 #endif
 
+/* Determin whether the target runtime library is Bionic */
+#ifndef TARGET_HAS_BIONIC
+#define TARGET_HAS_BIONIC 0
+#endif
+
 /* Indicate that CLZ and CTZ are undefined at zero.  */
 #ifndef CLZ_DEFINED_VALUE_AT_ZERO
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  0
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2914f10326f..42e07e0eca9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -5525,7 +5525,9 @@ Dump after live range splitting.
 @opindex fdump-rtl-dfinish
 These dumps are defined but always produce empty files.
 
-@item -fdump-rtl-all
+@item -da
+@itemx -fdump-rtl-all
+@opindex da
 @opindex fdump-rtl-all
 Produce all the dumps listed above.
 
@@ -5542,11 +5544,6 @@ normal output.
 @opindex dH
 Produce a core dump whenever an error occurs.
 
-@item -dm
-@opindex dm
-Print statistics on memory usage, at the end of the run, to
-standard error.
-
 @item -dp
 @opindex dp
 Annotate the assembler output with a comment indicating which
@@ -11468,6 +11465,10 @@ or @code{STS}. This offset depends on the device architecture and has
 to be subtracted from the RAM address in order to get the
 respective I/O@tie{}address.
 
+@item __WITH_AVRLIBC__
+The compiler is configured to be used together with AVR-Libc.
+See the @code{--with-avrlibc} configure option.
+
 @end table
 
 @node Blackfin Options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index c4eb355e253..386db196820 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3588,7 +3588,7 @@ Register B14 (aka DP).
 @itemx R07
 @itemx R08
 @itemx R09
-@itemx R010
+@itemx R10
 Each of these represents a register constraint for an individual
 register, from r0 to r10.
 
@@ -3666,7 +3666,7 @@ The integer constant 0xffffffff00000000.
 @itemx R07
 @itemx R08
 @itemx R09
-@itemx R010
+@itemx R10
 Each of these represents a register constraint for an individual
 register, from r0 to r10.
 
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 757678dc2df..bfdcfd54238 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2012-09-08  Mikael Morin  <mikael@gcc.gnu.org>
+
+	PR fortran/54208
+	* simplify.c (simplify_bound_dim): Resolve array spec before
+	proceeding with simplification.
+
 2012-07-06  Mikael Morin  <mikael@gcc.gnu.org>
 
 	PR fortran/53732
diff --git a/gcc/fortran/simplify.c b/gcc/fortran/simplify.c
index 706dab440ce..86de9cd6187 100644
--- a/gcc/fortran/simplify.c
+++ b/gcc/fortran/simplify.c
@@ -3255,6 +3255,9 @@ simplify_bound_dim (gfc_expr *array, gfc_expr *kind, int d, int upper,
   gcc_assert (array->expr_type == EXPR_VARIABLE);
   gcc_assert (as);
 
+  if (gfc_resolve_array_spec (as, 0) == FAILURE)
+    return NULL;
+
   /* The last dimension of an assumed-size array is special.  */
   if ((!coarray && d == as->rank && as->type == AS_ASSUMED_SIZE && !upper)
       || (coarray && d == as->rank + as->corank
diff --git a/gcc/function.c b/gcc/function.c
index 7c578791498..f16b5ef16b1 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -2975,11 +2975,26 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
 	  && insn_operand_matches (icode, 1, op1))
 	{
 	  enum rtx_code code = unsignedp ? ZERO_EXTEND : SIGN_EXTEND;
-	  rtx insn, insns;
+	  rtx insn, insns, t = op1;
 	  HARD_REG_SET hardregs;
 
 	  start_sequence ();
-	  insn = gen_extend_insn (op0, op1, promoted_nominal_mode,
+	  /* If op1 is a hard register that is likely spilled, first
+	     force it into a pseudo, otherwise combiner might extend
+	     its lifetime too much.  */
+	  if (GET_CODE (t) == SUBREG)
+	    t = SUBREG_REG (t);
+	  if (REG_P (t)
+	      && HARD_REGISTER_P (t)
+	      && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (t))
+	      && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (t))))
+	    {
+	      t = gen_reg_rtx (GET_MODE (op1));
+	      emit_move_insn (t, op1);
+	    }
+	  else
+	    t = op1;
+	  insn = gen_extend_insn (op0, t, promoted_nominal_mode,
 				  data->passed_mode, unsignedp);
 	  emit_insn (insn);
 	  insns = get_insns ();
diff --git a/gcc/gimplify.c b/gcc/gimplify.c
index 9249e42c188..a10d17e10da 100644
--- a/gcc/gimplify.c
+++ b/gcc/gimplify.c
@@ -3730,7 +3730,8 @@ optimize_compound_literals_in_ctor (tree orig_ctor)
 
 	  if (!TREE_ADDRESSABLE (value)
 	      && !TREE_ADDRESSABLE (decl)
-	      && init)
+	      && init
+	      && TREE_CODE (init) == CONSTRUCTOR)
 	    newval = optimize_compound_literals_in_ctor (init);
 	}
       if (newval == value)
diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc
index a2ac98703b4..f57ca411885 100644
--- a/gcc/go/gofrontend/expressions.cc
+++ b/gcc/go/gofrontend/expressions.cc
@@ -5084,7 +5084,7 @@ Binary_expression::do_lower(Gogo* gogo, Named_object*,
 						     &right_nc, location,
 						     &result))
 	      return this;
-	    return Expression::make_cast(Type::lookup_bool_type(),
+	    return Expression::make_cast(Type::make_boolean_type(),
 					 Expression::make_boolean(result,
 								  location),
 					 location);
@@ -5115,10 +5115,7 @@ Binary_expression::do_lower(Gogo* gogo, Named_object*,
 	    {
 	      int cmp = left_string.compare(right_string);
 	      bool r = Binary_expression::cmp_to_bool(op, cmp);
-	      return Expression::make_cast(Type::lookup_bool_type(),
-					   Expression::make_boolean(r,
-								    location),
-					   location);
+	      return Expression::make_boolean(r, location);
 	    }
 	}
     }
@@ -5336,15 +5333,15 @@ Binary_expression::do_type()
 
   switch (this->op_)
     {
-    case OPERATOR_OROR:
-    case OPERATOR_ANDAND:
     case OPERATOR_EQEQ:
     case OPERATOR_NOTEQ:
     case OPERATOR_LT:
     case OPERATOR_LE:
     case OPERATOR_GT:
     case OPERATOR_GE:
-      return Type::lookup_bool_type();
+      if (this->type_ == NULL)
+	this->type_ = Type::make_boolean_type();
+      return this->type_;
 
     case OPERATOR_PLUS:
     case OPERATOR_MINUS:
@@ -5355,6 +5352,8 @@ Binary_expression::do_type()
     case OPERATOR_MOD:
     case OPERATOR_AND:
     case OPERATOR_BITCLEAR:
+    case OPERATOR_OROR:
+    case OPERATOR_ANDAND:
       {
 	Type* type;
 	if (!Binary_expression::operation_type(this->op_,
@@ -5462,6 +5461,16 @@ Binary_expression::do_determine_type(const Type_context* context)
     }
 
   this->right_->determine_type(&subcontext);
+
+  if (is_comparison)
+    {
+      if (this->type_ != NULL && !this->type_->is_abstract())
+	;
+      else if (context->type != NULL && context->type->is_boolean_type())
+	this->type_ = context->type;
+      else if (!context->may_be_abstract)
+	this->type_ = Type::lookup_bool_type();
+    }
 }
 
 // Report an error if the binary operator OP does not support TYPE.
@@ -5673,7 +5682,7 @@ Binary_expression::do_get_tree(Translate_context* context)
     case OPERATOR_LE:
     case OPERATOR_GT:
     case OPERATOR_GE:
-      return Expression::comparison_tree(context, this->op_,
+      return Expression::comparison_tree(context, this->type_, this->op_,
 					 this->left_->type(), left,
 					 this->right_->type(), right,
 					 this->location());
@@ -6134,8 +6143,8 @@ Expression::make_binary(Operator op, Expression* left, Expression* right,
 // Implement a comparison.
 
 tree
-Expression::comparison_tree(Translate_context* context, Operator op,
-			    Type* left_type, tree left_tree,
+Expression::comparison_tree(Translate_context* context, Type* result_type,
+			    Operator op, Type* left_type, tree left_tree,
 			    Type* right_type, tree right_tree,
 			    Location location)
 {
@@ -6376,7 +6385,13 @@ Expression::comparison_tree(Translate_context* context, Operator op,
   if (left_tree == error_mark_node || right_tree == error_mark_node)
     return error_mark_node;
 
-  tree ret = fold_build2(code, boolean_type_node, left_tree, right_tree);
+  tree result_type_tree;
+  if (result_type == NULL)
+    result_type_tree = boolean_type_node;
+  else
+    result_type_tree = type_to_tree(result_type->get_backend(context->gogo()));
+
+  tree ret = fold_build2(code, result_type_tree, left_tree, right_tree);
   if (CAN_HAVE_LOCATION_P(ret))
     SET_EXPR_LOCATION(ret, location.gcc_location());
   return ret;
@@ -12923,26 +12938,8 @@ Type_guard_expression::do_traverse(Traverse* traverse)
 void
 Type_guard_expression::do_check_types(Gogo*)
 {
-  // 6g permits using a type guard with unsafe.pointer; we are
-  // compatible.
   Type* expr_type = this->expr_->type();
-  if (expr_type->is_unsafe_pointer_type())
-    {
-      if (this->type_->points_to() == NULL
-	  && (this->type_->integer_type() == NULL
-	      || (this->type_->forwarded()
-		  != Type::lookup_integer_type("uintptr"))))
-	this->report_error(_("invalid unsafe.Pointer conversion"));
-    }
-  else if (this->type_->is_unsafe_pointer_type())
-    {
-      if (expr_type->points_to() == NULL
-	  && (expr_type->integer_type() == NULL
-	      || (expr_type->forwarded()
-		  != Type::lookup_integer_type("uintptr"))))
-	this->report_error(_("invalid unsafe.Pointer conversion"));
-    }
-  else if (expr_type->interface_type() == NULL)
+  if (expr_type->interface_type() == NULL)
     {
       if (!expr_type->is_error() && !this->type_->is_error())
 	this->report_error(_("type assertion only valid for interface types"));
@@ -12975,23 +12972,10 @@ Type_guard_expression::do_check_types(Gogo*)
 tree
 Type_guard_expression::do_get_tree(Translate_context* context)
 {
-  Gogo* gogo = context->gogo();
   tree expr_tree = this->expr_->get_tree(context);
   if (expr_tree == error_mark_node)
     return error_mark_node;
-  Type* expr_type = this->expr_->type();
-  if ((this->type_->is_unsafe_pointer_type()
-       && (expr_type->points_to() != NULL
-	   || expr_type->integer_type() != NULL))
-      || (expr_type->is_unsafe_pointer_type()
-	  && this->type_->points_to() != NULL))
-    return convert_to_pointer(type_to_tree(this->type_->get_backend(gogo)),
-			      expr_tree);
-  else if (expr_type->is_unsafe_pointer_type()
-	   && this->type_->integer_type() != NULL)
-    return convert_to_integer(type_to_tree(this->type_->get_backend(gogo)),
-			      expr_tree);
-  else if (this->type_->interface_type() != NULL)
+  if (this->type_->interface_type() != NULL)
     return Expression::convert_interface_to_interface(context, this->type_,
 						      this->expr_->type(),
 						      expr_tree, true,
diff --git a/gcc/go/gofrontend/expressions.h b/gcc/go/gofrontend/expressions.h
index 156cf3ceea3..eea141fe776 100644
--- a/gcc/go/gofrontend/expressions.h
+++ b/gcc/go/gofrontend/expressions.h
@@ -623,9 +623,9 @@ class Expression
   // Return a tree implementing the comparison LHS_TREE OP RHS_TREE.
   // TYPE is the type of both sides.
   static tree
-  comparison_tree(Translate_context*, Operator op, Type* left_type,
-		  tree left_tree, Type* right_type, tree right_tree,
-		  Location);
+  comparison_tree(Translate_context*, Type* result_type, Operator op,
+		  Type* left_type, tree left_tree, Type* right_type,
+		  tree right_tree, Location);
 
   // Return a tree for the multi-precision integer VAL in TYPE.
   static tree
@@ -1149,7 +1149,7 @@ class Binary_expression : public Expression
   Binary_expression(Operator op, Expression* left, Expression* right,
 		    Location location)
     : Expression(EXPRESSION_BINARY, location),
-      op_(op), left_(left), right_(right)
+      op_(op), left_(left), right_(right), type_(NULL)
   { }
 
   // Return the operator.
@@ -1280,6 +1280,8 @@ class Binary_expression : public Expression
   Expression* left_;
   // The right hand side operand.
   Expression* right_;
+  // The type of a comparison operation.
+  Type* type_;
 };
 
 // A call expression.  The go statement needs to dig inside this.
diff --git a/gcc/go/gofrontend/statements.cc b/gcc/go/gofrontend/statements.cc
index 7f91e553a4d..fa7f20836ad 100644
--- a/gcc/go/gofrontend/statements.cc
+++ b/gcc/go/gofrontend/statements.cc
@@ -4192,55 +4192,41 @@ Type_switch_statement::do_lower(Gogo*, Named_object*, Block* enclosing,
 		    ? this->var_->var_value()->type()
 		    : this->expr_->type());
 
+  if (val_type->interface_type() == NULL)
+    {
+      if (!val_type->is_error())
+	this->report_error(_("cannot type switch on non-interface value"));
+      return Statement::make_error_statement(loc);
+    }
+
   // var descriptor_temp DESCRIPTOR_TYPE
   Type* descriptor_type = Type::make_type_descriptor_ptr_type();
   Temporary_statement* descriptor_temp =
     Statement::make_temporary(descriptor_type, NULL, loc);
   b->add_statement(descriptor_temp);
 
-  if (val_type->interface_type() == NULL)
-    {
-      // Doing a type switch on a non-interface type.  Should we issue
-      // a warning for this case?
-      Expression* lhs = Expression::make_temporary_reference(descriptor_temp,
-							     loc);
-      Expression* rhs;
-      if (val_type->is_nil_type())
-	rhs = Expression::make_nil(loc);
-      else
-	{
-	  if (val_type->is_abstract())
-	    val_type = val_type->make_non_abstract_type();
-	  rhs = Expression::make_type_descriptor(val_type, loc);
-	}
-      Statement* s = Statement::make_assignment(lhs, rhs, loc);
-      b->add_statement(s);
-    }
+  // descriptor_temp = ifacetype(val_temp) FIXME: This should be
+  // inlined.
+  bool is_empty = val_type->interface_type()->is_empty();
+  Expression* ref;
+  if (this->var_ == NULL)
+    ref = this->expr_;
   else
-    {
-      // descriptor_temp = ifacetype(val_temp)
-      // FIXME: This should be inlined.
-      bool is_empty = val_type->interface_type()->is_empty();
-      Expression* ref;
-      if (this->var_ == NULL)
-	ref = this->expr_;
-      else
-	ref = Expression::make_var_reference(this->var_, loc);
-      Expression* call = Runtime::make_call((is_empty
-					     ? Runtime::EFACETYPE
-					     : Runtime::IFACETYPE),
-					    loc, 1, ref);
-      Temporary_reference_expression* lhs =
-	Expression::make_temporary_reference(descriptor_temp, loc);
-      lhs->set_is_lvalue();
-      Statement* s = Statement::make_assignment(lhs, call, loc);
-      b->add_statement(s);
-    }
+    ref = Expression::make_var_reference(this->var_, loc);
+  Expression* call = Runtime::make_call((is_empty
+					 ? Runtime::EFACETYPE
+					 : Runtime::IFACETYPE),
+					loc, 1, ref);
+  Temporary_reference_expression* lhs =
+    Expression::make_temporary_reference(descriptor_temp, loc);
+  lhs->set_is_lvalue();
+  Statement* s = Statement::make_assignment(lhs, call, loc);
+  b->add_statement(s);
 
   if (this->clauses_ != NULL)
     this->clauses_->lower(val_type, b, descriptor_temp, this->break_label());
 
-  Statement* s = Statement::make_unnamed_label_statement(this->break_label_);
+  s = Statement::make_unnamed_label_statement(this->break_label_);
   b->add_statement(s);
 
   return Statement::make_block_statement(b, loc);
diff --git a/gcc/graphite-sese-to-poly.c b/gcc/graphite-sese-to-poly.c
index d9bcf278307..9167a728089 100644
--- a/gcc/graphite-sese-to-poly.c
+++ b/gcc/graphite-sese-to-poly.c
@@ -3229,6 +3229,7 @@ scop_ivs_can_be_represented (scop_p scop)
   loop_iterator li;
   loop_p loop;
   gimple_stmt_iterator psi;
+  bool result = true;
 
   FOR_EACH_LOOP (li, loop, 0)
     {
@@ -3244,11 +3245,16 @@ scop_ivs_can_be_represented (scop_p scop)
 
 	  if (TYPE_UNSIGNED (type)
 	      && TYPE_PRECISION (type) >= TYPE_PRECISION (long_long_integer_type_node))
-	    return false;
+	    {
+	      result = false;
+	      break;
+	    }
 	}
+      if (!result)
+	FOR_EACH_LOOP_BREAK (li);
     }
 
-  return true;
+  return result;
 }
 
 /* Builds the polyhedral representation for a SESE region.  */
diff --git a/gcc/ipa-pure-const.c b/gcc/ipa-pure-const.c
index e8b21f9fc6b..e21805e9c23 100644
--- a/gcc/ipa-pure-const.c
+++ b/gcc/ipa-pure-const.c
@@ -803,7 +803,7 @@ end:
 		    if (dump_file)
 		      fprintf (dump_file, "    can not prove finiteness of loop %i\n", loop->num);
 		    l->looping =true;
-		    break;
+		    FOR_EACH_LOOP_BREAK (li);
 		  }
 	      scev_finalize ();
 	    }
diff --git a/gcc/ipa-split.c b/gcc/ipa-split.c
index 9dddf393fa7..061bafd885f 100644
--- a/gcc/ipa-split.c
+++ b/gcc/ipa-split.c
@@ -1239,6 +1239,7 @@ split_function (struct split_point *split_point)
       }
   call = gimple_build_call_vec (node->decl, args_to_pass);
   gimple_set_block (call, DECL_INITIAL (current_function_decl));
+  VEC_free (tree, heap, args_to_pass);
 
   /* We avoid address being taken on any variable used by split part,
      so return slot optimization is always possible.  Moreover this is
diff --git a/gcc/ira-build.c b/gcc/ira-build.c
index 78d0b36acda..79bbe91ff69 100644
--- a/gcc/ira-build.c
+++ b/gcc/ira-build.c
@@ -1843,15 +1843,21 @@ loop_with_complex_edge_p (struct loop *loop)
   edge_iterator ei;
   edge e;
   VEC (edge, heap) *edges;
+  bool res;
 
   FOR_EACH_EDGE (e, ei, loop->header->preds)
     if (e->flags & EDGE_EH)
       return true;
   edges = get_loop_exit_edges (loop);
+  res = false;
   FOR_EACH_VEC_ELT (edge, edges, i, e)
     if (e->flags & EDGE_COMPLEX)
-      return true;
-  return false;
+      {
+	res = true;
+	break;
+      }
+  VEC_free (edge, heap, edges);
+  return res;
 }
 #endif
 
diff --git a/gcc/jump.c b/gcc/jump.c
index d49b58ef1b1..38ed2d88eef 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -1260,9 +1260,9 @@ delete_related_insns (rtx insn)
 	  && GET_CODE (PATTERN (insn)) == SEQUENCE
 	  && CALL_P (XVECEXP (PATTERN (insn), 0, 0))))
     {
-      rtx p = insn;
+      rtx p;
 
-      for (p = NEXT_INSN (p);
+      for (p = next && INSN_DELETED_P (next) ? NEXT_INSN (next) : next;
 	   p && NOTE_P (p);
 	   p = NEXT_INSN (p))
 	if (NOTE_KIND (p) == NOTE_INSN_CALL_ARG_LOCATION)
diff --git a/gcc/modulo-sched.c b/gcc/modulo-sched.c
index b1b1af33b26..54b074d56a1 100644
--- a/gcc/modulo-sched.c
+++ b/gcc/modulo-sched.c
@@ -1416,7 +1416,7 @@ sms_schedule (void)
           if (dump_file)
             fprintf (dump_file, "SMS reached max limit... \n");
 
-          break;
+	  FOR_EACH_LOOP_BREAK (li);
         }
 
       if (dump_file)
diff --git a/gcc/omp-low.c b/gcc/omp-low.c
index 4247a80caa1..8245b820fef 100644
--- a/gcc/omp-low.c
+++ b/gcc/omp-low.c
@@ -6859,6 +6859,9 @@ lower_omp_1 (gimple_stmt_iterator *gsi_p, omp_context *ctx)
       lower_omp (gimple_try_eval (stmt), ctx);
       lower_omp (gimple_try_cleanup (stmt), ctx);
       break;
+    case GIMPLE_TRANSACTION:
+      lower_omp (gimple_transaction_body (stmt), ctx);
+      break;
     case GIMPLE_BIND:
       lower_omp (gimple_bind_body (stmt), ctx);
       break;
diff --git a/gcc/params.def b/gcc/params.def
index 27db78275e1..6c0b1a955d0 100644
--- a/gcc/params.def
+++ b/gcc/params.def
@@ -638,11 +638,12 @@ DEFPARAM(PARAM_MAX_LAST_VALUE_RTL,
 
 /* INTEGER_CST nodes are shared for values [{-1,0} .. N) for
    {signed,unsigned} integral types.  This determines N.
-   Experimentation shows 256 to be a good value.  */
+   Experimentation shows 251 to be a good value that generates the
+   least amount of garbage for allocating the TREE_VEC storage.  */
 DEFPARAM (PARAM_INTEGER_SHARE_LIMIT,
 	  "integer-share-limit",
 	  "The upper bound for sharing integer constants",
-	  256, 2, 2)
+	  251, 2, 2)
 
 /* Incremental SSA updates for virtual operands may be very slow if
    there is a large number of mappings to process.  In those cases, it
diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c
index c53d2e1a8e9..e74fee248b5 100644
--- a/gcc/sel-sched-ir.c
+++ b/gcc/sel-sched-ir.c
@@ -1,5 +1,5 @@
 /* Instruction scheduling pass.  Selective scheduler and pipeliner.
-   Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
+   Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011, 2012
    Free Software Foundation, Inc.
 
 This file is part of GCC.
@@ -3680,6 +3680,22 @@ maybe_tidy_empty_bb (basic_block bb)
   FOR_EACH_EDGE (e, ei, bb->preds)
     if (e->flags & EDGE_COMPLEX)
       return false;
+    else if (e->flags & EDGE_FALLTHRU)
+      {
+	rtx note;
+	/* If prev bb ends with asm goto, see if any of the
+	   ASM_OPERANDS_LABELs don't point to the fallthru
+	   label.  Do not attempt to redirect it in that case.  */
+	if (JUMP_P (BB_END (e->src))
+	    && (note = extract_asm_operands (PATTERN (BB_END (e->src)))))
+	  {
+	    int i, n = ASM_OPERANDS_LABEL_LENGTH (note);
+
+	    for (i = 0; i < n; ++i)
+	      if (XEXP (ASM_OPERANDS_LABEL (note, i), 0) == BB_HEAD (bb))
+		return false;
+	  }
+      }
 
   free_data_sets (bb);
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 731fd9663bd..3463dd05f67 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,120 @@
+2012-09-08  Mikael Morin  <mikael@gcc.gnu.org>
+
+	PR fortran/54208
+	* gfortran.dg/bound_simplification_3.f90: New test.
+
+2012-09-07  Richard Guenther  <rguenther@suse.de>
+
+	Backport from mainline
+	2012-07-13  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/53922
+	* gcc.dg/torture/pr53922.c: New testcase.
+
+2012-09-07  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc.dg/pr44194-1.c: Skip on Alpha and adjust regexp for SPARC64.
+
+2012-09-07  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from mainline
+	2012-09-06  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/54455
+	* gcc.dg/54455.c: New test.
+
+2012-09-06  Andrew Pinski  <apinski@cavium.com>
+
+	PR tree-opt/54494
+	* gcc.dg/tree-ssa/strlen-1.c: New testcase.
+
+2012-09-05  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/54486
+	* c-c++-common/pr54486.c: New test.
+
+2012-09-05  Joey Ye  <joey.ye@arm.com>
+
+	Backported from trunk
+	2012-08-28  Joey Ye  <joey.ye@arm.com>
+
+	* gcc.dg/tree-ssa/ssa-dom-thread-3.c: Add -fno-short-enums.
+
+2012-09-03  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from mainline
+	2012-09-01  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/54436
+	* gcc.dg/torture/pr54436.c: New test.
+
+	2012-08-31  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/54428
+	* gcc.c-torture/compile/pr54428.c: New test.
+
+	2012-08-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/54363
+	* gcc.dg/pr54363.c: New test.
+
+2012-08-31  Ollie Wild  <aaw@google.com>
+
+	PR c++/54197
+	* g++.dg/init/lifetime3.C: New test.
+
+2012-08-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-08-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/46254
+	* gcc.target/i386/pr46254.c: New test.
+
+2012-08-20  Patrick Marlier  <patrick.marlier@gmail.com>
+
+	Backported from trunk
+	2012-08-20  Patrick Marlier  <patrick.marlier@gmail.com>
+
+	PR middle-end/53992
+	* gcc.dg/gomp/pr53992.c: New test.
+
+2012-08-13  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from trunk
+	2012-07-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/53942
+	* gcc.dg/pr53942.c: New test.
+
+2012-08-10  Ulrich Weigand  <ulrich.weigand@linaro.org>
+
+	Backport from mainline
+	2012-07-30  Ulrich Weigand  <ulrich.weigand@linaro.org>
+
+	* lib/target-supports.exp
+	(check_effective_target_vect_natural_alignment): New function.
+	* gcc.dg/align-2.c: Only run on targets with natural alignment
+	of vector types.
+	* gcc.dg/vect/slp-25.c: Adjust tests for targets without natural
+	alignment of vector types.
+
+2012-08-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from mainline
+	2012-08-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR rtl-optimization/54157
+	* gcc.target/i386/pr54157.c: New file.
+
+2012-08-01  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backport from mainline
+	2012-03-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/52530
+	* gcc.dg/torture/pr52530.c: New test.
+
 2012-07-27  Anna Tikhonova  <anna.tikhonova@intel.com>
 
 	* gcc.dg/20020201-1.c: Remove declarations for exit, abort,
diff --git a/gcc/testsuite/c-c++-common/pr54486.c b/gcc/testsuite/c-c++-common/pr54486.c
new file mode 100644
index 00000000000..e8125fcf398
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/pr54486.c
@@ -0,0 +1,32 @@
+/* PR middle-end/54486 */
+/* { dg-do compile } */
+/* { dg-options "-Wformat" } */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+typedef __SIZE_TYPE__ size_t;
+extern int printf (const char *, ...);
+extern size_t strspn (const char *, const char *);
+extern size_t strcspn (const char *, const char *);
+extern size_t strlen (const char *);
+#ifdef __cplusplus
+}
+#endif
+
+void
+foo (void)
+{
+  printf ("%zu\n", strspn ("abc", "abcdefg"));
+  printf ("%zu\n", (size_t) strspn ("abc", "abcdefg"));
+  printf ("%zu\n", __builtin_strspn ("abc", "abcdefg"));
+  printf ("%zu\n", (size_t) __builtin_strspn ("abc", "abcdefg"));
+  printf ("%zu\n", strcspn ("abc", "abcdefg"));
+  printf ("%zu\n", (size_t) strcspn ("abc", "abcdefg"));
+  printf ("%zu\n", __builtin_strcspn ("abc", "abcdefg"));
+  printf ("%zu\n", (size_t) __builtin_strcspn ("abc", "abcdefg"));
+  printf ("%zu\n", strlen ("abc"));
+  printf ("%zu\n", (size_t) strlen ("abc"));
+  printf ("%zu\n", __builtin_strlen ("abc"));
+  printf ("%zu\n", (size_t) __builtin_strlen ("abc"));
+}
diff --git a/gcc/testsuite/g++.dg/init/lifetime3.C b/gcc/testsuite/g++.dg/init/lifetime3.C
new file mode 100644
index 00000000000..d099699f868
--- /dev/null
+++ b/gcc/testsuite/g++.dg/init/lifetime3.C
@@ -0,0 +1,37 @@
+// PR c++/26714
+// { dg-do run }
+
+extern "C" void abort();
+
+bool ok = false;
+struct A {
+  A() { }
+  ~A() { if (!ok) abort(); }
+};
+
+struct B {
+  static A foo() { return A(); }
+};
+
+B b_g;
+
+struct scoped_ptr {
+  B* operator->() const { return &b_g; }
+  B* get() const { return &b_g; }
+};
+
+B *get() { return &b_g; }
+
+int main()
+{
+  scoped_ptr f;
+  const A& ref1 = f->foo();
+  const A& ref2 = f.get()->foo();
+  const A& ref3 = get()->foo();
+  const A& ref4 = B::foo();
+  B *pf = f.get();
+  const A& ref5 = pf->foo();
+
+
+  ok = true;
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr54428.c b/gcc/testsuite/gcc.c-torture/compile/pr54428.c
new file mode 100644
index 00000000000..84a5dbd82bd
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr54428.c
@@ -0,0 +1,9 @@
+/* PR c/54428 */
+
+typedef double _Complex C;
+
+C
+foo (C x, C y, double z, C w)
+{
+  return y - z * __builtin_cpow (x, 75) * w;
+}
diff --git a/gcc/testsuite/gcc.dg/54455.c b/gcc/testsuite/gcc.dg/54455.c
new file mode 100644
index 00000000000..de68a53e233
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/54455.c
@@ -0,0 +1,25 @@
+/* PR rtl-optimization/54455 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -fschedule-insns -fselective-scheduling --param max-sched-extend-regions-iters=2" } */
+
+extern void fn1 (void), fn2 (void);
+
+static inline __attribute__((always_inline)) int
+foo (int *x, long y)
+{
+  asm goto ("" : : "r" (x), "r" (y) : "memory" : lab);
+  return 0;
+lab:
+  return 1;
+}
+
+void
+bar (int *x)
+{
+  if (foo (x, 23))
+    fn1 ();
+  else
+    fn2 ();
+
+  foo (x, 2);
+}
diff --git a/gcc/testsuite/gcc.dg/gomp/pr53992.c b/gcc/testsuite/gcc.dg/gomp/pr53992.c
new file mode 100644
index 00000000000..4d5af3ce785
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/gomp/pr53992.c
@@ -0,0 +1,21 @@
+/* PR middle-end/53992 */
+/* { dg-do compile } */
+/* { dg-options "-fgnu-tm -fopenmp" } */
+/* { dg-require-effective-target fgnu_tm } */
+
+int main() {
+    long data[10000];
+    long i, min=10000;
+    for (i=0; i<10000; i++) data[i] = -i;
+            
+#pragma omp parallel for
+    for (i=0; i<10000; i++) {
+        __transaction_atomic
+        {
+            if (data[i] < min)
+                min = data[i];
+        }
+    }
+
+    return !(min == -9999);
+}
diff --git a/gcc/testsuite/gcc.dg/pr44194-1.c b/gcc/testsuite/gcc.dg/pr44194-1.c
index d251bf1b941..d993a42a02b 100644
--- a/gcc/testsuite/gcc.dg/pr44194-1.c
+++ b/gcc/testsuite/gcc.dg/pr44194-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { { { i?86-*-* x86_64-*-* } && x32 } || lp64 } && { ! s390*-*-* } } } } */
+/* { dg-do compile { target { { { { { i?86-*-* x86_64-*-* } && x32 } || lp64 } && { ! s390*-*-* } } &&  { ! alpha*-*-* } } } } */
 /* { dg-options "-O2 -fdump-rtl-dse1" } */
 /* Restricting to 64-bit targets since 32-bit targets return
    structures in memory.  */
@@ -10,5 +10,5 @@ void func() {
   struct ints s = foo();
   bar(s.a, s.b);
 }
-/* { dg-final { scan-rtl-dump "global deletions = 2"  "dse1" } } */
+/* { dg-final { scan-rtl-dump "global deletions = (2|3)"  "dse1" } } */
 /* { dg-final { cleanup-rtl-dump "dse1" } } */
diff --git a/gcc/testsuite/gcc.dg/pr52530.c b/gcc/testsuite/gcc.dg/pr52530.c
new file mode 100644
index 00000000000..f7cdf1a63b3
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr52530.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+
+extern void abort (void);
+
+#if __SIZEOF_INT__ > 2
+struct foo
+{
+ int *f;
+ int i;
+};
+
+int baz;
+#else
+struct foo
+{
+ long *f;
+ long i;
+};
+
+long baz;
+#endif
+
+void __attribute__ ((noinline))
+bar (struct foo x)
+{
+ *(x.f) = x.i;
+}
+
+int
+main ()
+{
+  struct foo x = { &baz, 0xdeadbeef };
+
+  bar (x);
+
+  if (baz != 0xdeadbeef)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/pr53942.c b/gcc/testsuite/gcc.dg/pr53942.c
new file mode 100644
index 00000000000..6a51d2673dd
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr53942.c
@@ -0,0 +1,34 @@
+/* PR rtl-optimization/53942 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-additional-options "-mtune=pentium2" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
+
+struct S
+{
+  unsigned short w[3];
+  unsigned int x, y;
+};
+
+struct S *baz (void);
+
+__attribute__ ((noinline))
+static unsigned char
+foo (struct S *x, unsigned char y)
+{
+  unsigned char c = 0;
+  unsigned char v = x->w[0];
+  c |= v;
+  v = ((x->w[1]) & (1 << y)) ? 1 : 0;
+  c |= v << 1;
+  v = ((x->w[2]) & 0xff) & (1 << y);
+  c |= v << 2;
+  return c;
+}
+
+void
+bar (void)
+{
+  struct S *s = baz ();
+  s->x = foo (s, 6);
+  s->y = foo (s, 7);
+}
diff --git a/gcc/testsuite/gcc.dg/pr54363.c b/gcc/testsuite/gcc.dg/pr54363.c
new file mode 100644
index 00000000000..aea0f9057b0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr54363.c
@@ -0,0 +1,12 @@
+/* PR c/54363 */
+/* { dg-do compile } */
+/* { dg-options "-std=gnu99" } */
+
+struct S { char **a; };
+
+void
+test (void)
+{
+  struct S b = { .a = (char **) { "a", "b" } }; /* { dg-warning "(initialization|excess elements)" } */
+  struct S c = { .a = (char *[]) { "a", "b" } };
+}
diff --git a/gcc/testsuite/gcc.dg/torture/pr53922.c b/gcc/testsuite/gcc.dg/torture/pr53922.c
new file mode 100644
index 00000000000..e42d1c788c7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr53922.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-weak "" } */
+
+int x(int a)
+{
+  return a;
+}
+int y(int a) __attribute__ ((weak));
+int g = 0;
+int main()
+{
+  int (*scan_func)(int);
+  if (g)
+    scan_func = x;
+  else
+    scan_func = y;
+
+  if (scan_func)
+    g = scan_func(10);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/torture/pr54436.c b/gcc/testsuite/gcc.dg/torture/pr54436.c
new file mode 100644
index 00000000000..4bce3240906
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr54436.c
@@ -0,0 +1,38 @@
+/* PR target/54436 */
+/* { dg-do assemble } */
+
+#if __SIZEOF_SHORT__ == 2 && __SIZEOF_LONG_LONG__ == 8
+static inline unsigned short
+baz (unsigned short *x)
+{
+  union U { unsigned short a; unsigned char b[2]; } u = { *x };
+  u.b[0] = ((u.b[0] * 0x0802ULL & 0x22110ULL)
+	    | (u.b[0] * 0x8020ULL & 0x88440ULL)) * 0x10101ULL >> 16;
+  u.b[1] = ((u.b[1] * 0x0802ULL & 0x22110ULL)
+	    | (u.b[1] * 0x8020ULL & 0x88440ULL)) * 0x10101ULL >> 16;
+  unsigned char t = u.b[0];
+  u.b[0] = u.b[1];
+  u.b[1] = t;
+  return u.a;
+}
+
+static inline unsigned long long
+bar (unsigned long long *x)
+{
+  union U { unsigned long long a; unsigned short b[4]; } u = { *x };
+  u.b[0] = baz (&u.b[0]);
+  return u.a;
+}
+
+void
+foo (void)
+{
+  unsigned long long l = -1ULL;
+  __asm volatile ("" : : "r" (bar (&l)));
+}
+#else
+void
+foo (void)
+{
+}
+#endif
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-3.c
index d851bf23fe8..d67f8692862 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-3.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-3.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */ 
-/* { dg-options "-O2 -fdump-tree-dom1-details" } */
+/* { dg-options "-O2 -fdump-tree-dom1-details -fno-short-enums" } */
+
 extern void abort (void) __attribute__ ((__noreturn__));
 union tree_node;
 typedef union tree_node *tree;
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/strlen-1.c b/gcc/testsuite/gcc.dg/tree-ssa/strlen-1.c
new file mode 100644
index 00000000000..f6ff3e1570f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/strlen-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+extern const unsigned long base;
+static inline void wreg(unsigned char val, unsigned long addr) __attribute__((always_inline));
+static inline void wreg(unsigned char val, unsigned long addr)
+{
+   *((volatile unsigned char *) (__SIZE_TYPE__) (base + addr)) = val;
+}
+void wreg_twice(void)
+{
+   wreg(0, 42);
+   wreg(0, 42);
+}
+
+/* We should not remove the second null character store to (base+42) address. */
+/* { dg-final { scan-tree-dump-times " ={v} 0;" 2 "optimized" } }  */
+/* { dg-final { cleanup-tree-dump "optimized" } }  */
diff --git a/gcc/testsuite/gcc.target/i386/pr46254.c b/gcc/testsuite/gcc.target/i386/pr46254.c
new file mode 100644
index 00000000000..512287a5b39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr46254.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mcx16 -fpic -mcmodel=large" } */
+
+__int128 i;
+
+void test ()
+{
+  __sync_val_compare_and_swap (&i, i, i);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr54157.c b/gcc/testsuite/gcc.target/i386/pr54157.c
new file mode 100644
index 00000000000..59fcd792bd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr54157.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32 -ftree-vectorize" } */
+
+struct s2{
+  int n[24 -1][24 -1][24 -1];
+};
+
+struct test2{
+  struct s2 e;
+};
+
+struct test2 tmp2[4];
+
+void main1 ()
+{
+  int i,j;
+
+  for (i = 0; i < 24 -4; i++)
+      for (j = 0; j < 24 -4; j++)
+          tmp2[2].e.n[1][i][j] = 8;
+}
diff --git a/gcc/testsuite/gfortran.dg/bound_simplification_3.f90 b/gcc/testsuite/gfortran.dg/bound_simplification_3.f90
new file mode 100644
index 00000000000..de3a3dc8a94
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/bound_simplification_3.f90
@@ -0,0 +1,23 @@
+! { dg-do compile }
+! { dg-options "-fdump-tree-original" }
+!
+! PR fortran/54208
+! The I and J definitions used to raise an error because ARR's array spec
+! was resolved to late for the LBOUND and UBOUND calls to be simplified to
+! a constant.
+!
+! Contributed by Carlos A. Cruz <carlos.a.cruz@nasa.gov>
+
+program testit
+  integer, parameter :: n=2
+  integer, dimension(1-min(n,2)/2:n) :: arr
+  integer, parameter :: i=lbound(arr,1)
+  integer, parameter :: j=ubound(arr,1)
+  ! write(6,*) i, j
+  if (i /= 0) call abort
+  if (j /= 2) call abort
+end program testit
+
+! { dg-final { scan-tree-dump-times "bound" 0 "original" } }
+! { dg-final { scan-tree-dump-times "abort" 0 "original" } }
+! { dg-final { cleanup-tree-dump "original" } }
diff --git a/gcc/testsuite/go.test/test/named1.go b/gcc/testsuite/go.test/test/named1.go
index 499b77b9615..561d84a43dc 100644
--- a/gcc/testsuite/go.test/test/named1.go
+++ b/gcc/testsuite/go.test/test/named1.go
@@ -37,8 +37,8 @@ func main() {
 	asBool(true)
 	asBool(*&b)
 	asBool(Bool(true))
-	asBool(1 != 2) // ERROR "cannot use.*type bool.*as type Bool"
-	asBool(i < j)  // ERROR "cannot use.*type bool.*as type Bool"
+	asBool(1 != 2) // ok now
+	asBool(i < j)  // ok now
 
 	_, b = m[2] // ERROR "cannot .* bool.*type Bool"
 
diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c
index d8eb3a9c1fc..349e0b0186f 100644
--- a/gcc/tree-inline.c
+++ b/gcc/tree-inline.c
@@ -871,6 +871,7 @@ remap_gimple_op_r (tree *tp, int *walk_subtrees, void *data)
 			     ptr, TREE_OPERAND (*tp, 1));
 	  TREE_THIS_NOTRAP (*tp) = TREE_THIS_NOTRAP (old);
 	  TREE_THIS_VOLATILE (*tp) = TREE_THIS_VOLATILE (old);
+	  TREE_SIDE_EFFECTS (*tp) = TREE_SIDE_EFFECTS (old);
 	  TREE_NO_WARNING (*tp) = TREE_NO_WARNING (old);
 	  *walk_subtrees = 0;
 	  return NULL;
diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c
index 9cfab4e8cd0..897283c23ef 100644
--- a/gcc/tree-sra.c
+++ b/gcc/tree-sra.c
@@ -4777,6 +4777,8 @@ modify_function (struct cgraph_node *node, ipa_parm_adjustment_vec adjustments)
 
   new_node = cgraph_function_versioning (node, redirect_callers, NULL, NULL,
 					 false, NULL, NULL, "isra");
+  VEC_free (cgraph_edge_p, heap, redirect_callers);
+
   current_function_decl = new_node->decl;
   push_cfun (DECL_STRUCT_FUNCTION (new_node->decl));
 
diff --git a/gcc/tree-ssa-alias.c b/gcc/tree-ssa-alias.c
index e3a8ad01162..1b3981564d1 100644
--- a/gcc/tree-ssa-alias.c
+++ b/gcc/tree-ssa-alias.c
@@ -1886,7 +1886,7 @@ stmt_kills_ref_p (gimple stmt, tree ref)
 
 static bool
 maybe_skip_until (gimple phi, tree target, ao_ref *ref,
-		  tree vuse, bitmap *visited)
+		  tree vuse, bitmap *visited, bool abort_on_visited)
 {
   basic_block bb = gimple_bb (phi);
 
@@ -1904,8 +1904,9 @@ maybe_skip_until (gimple phi, tree target, ao_ref *ref,
 	{
 	  /* An already visited PHI node ends the walk successfully.  */
 	  if (bitmap_bit_p (*visited, SSA_NAME_VERSION (PHI_RESULT (def_stmt))))
-	    return true;
-	  vuse = get_continuation_for_phi (def_stmt, ref, visited);
+	    return !abort_on_visited;
+	  vuse = get_continuation_for_phi (def_stmt, ref,
+					   visited, abort_on_visited);
 	  if (!vuse)
 	    return false;
 	  continue;
@@ -1919,7 +1920,7 @@ maybe_skip_until (gimple phi, tree target, ao_ref *ref,
       if (gimple_bb (def_stmt) != bb)
 	{
 	  if (!bitmap_set_bit (*visited, SSA_NAME_VERSION (vuse)))
-	    return true;
+	    return !abort_on_visited;
 	  bb = gimple_bb (def_stmt);
 	}
       vuse = gimple_vuse (def_stmt);
@@ -1933,7 +1934,8 @@ maybe_skip_until (gimple phi, tree target, ao_ref *ref,
 
 static tree
 get_continuation_for_phi_1 (gimple phi, tree arg0, tree arg1,
-			    ao_ref *ref, bitmap *visited)
+			    ao_ref *ref, bitmap *visited,
+			    bool abort_on_visited)
 {
   gimple def0 = SSA_NAME_DEF_STMT (arg0);
   gimple def1 = SSA_NAME_DEF_STMT (arg1);
@@ -1946,14 +1948,14 @@ get_continuation_for_phi_1 (gimple phi, tree arg0, tree arg1,
 	       && dominated_by_p (CDI_DOMINATORS,
 				  gimple_bb (def1), gimple_bb (def0))))
     {
-      if (maybe_skip_until (phi, arg0, ref, arg1, visited))
+      if (maybe_skip_until (phi, arg0, ref, arg1, visited, abort_on_visited))
 	return arg0;
     }
   else if (gimple_nop_p (def1)
 	   || dominated_by_p (CDI_DOMINATORS,
 			      gimple_bb (def0), gimple_bb (def1)))
     {
-      if (maybe_skip_until (phi, arg1, ref, arg0, visited))
+      if (maybe_skip_until (phi, arg1, ref, arg0, visited, abort_on_visited))
 	return arg1;
     }
   /* Special case of a diamond:
@@ -1988,7 +1990,8 @@ get_continuation_for_phi_1 (gimple phi, tree arg0, tree arg1,
    be found.  */
 
 tree
-get_continuation_for_phi (gimple phi, ao_ref *ref, bitmap *visited)
+get_continuation_for_phi (gimple phi, ao_ref *ref, bitmap *visited,
+			  bool abort_on_visited)
 {
   unsigned nargs = gimple_phi_num_args (phi);
 
@@ -2025,7 +2028,8 @@ get_continuation_for_phi (gimple phi, ao_ref *ref, bitmap *visited)
       for (i = 0; i < nargs; ++i)
 	{
 	  arg1 = PHI_ARG_DEF (phi, i);
-	  arg0 = get_continuation_for_phi_1 (phi, arg0, arg1, ref, visited);
+	  arg0 = get_continuation_for_phi_1 (phi, arg0, arg1, ref, visited,
+					     abort_on_visited);
 	  if (!arg0)
 	    return NULL_TREE;
 	}
@@ -2061,6 +2065,7 @@ walk_non_aliased_vuses (ao_ref *ref, tree vuse,
 {
   bitmap visited = NULL;
   void *res;
+  bool translated = false;
 
   timevar_push (TV_ALIAS_STMT_WALK);
 
@@ -2077,7 +2082,7 @@ walk_non_aliased_vuses (ao_ref *ref, tree vuse,
       if (gimple_nop_p (def_stmt))
 	break;
       else if (gimple_code (def_stmt) == GIMPLE_PHI)
-	vuse = get_continuation_for_phi (def_stmt, ref, &visited);
+	vuse = get_continuation_for_phi (def_stmt, ref, &visited, translated);
       else
 	{
 	  if (stmt_may_clobber_ref_p_1 (def_stmt, ref))
@@ -2095,6 +2100,7 @@ walk_non_aliased_vuses (ao_ref *ref, tree vuse,
 	      else if (res != NULL)
 		break;
 	      /* Translation succeeded, continue walking.  */
+	      translated = true;
 	    }
 	  vuse = gimple_vuse (def_stmt);
 	}
diff --git a/gcc/tree-ssa-alias.h b/gcc/tree-ssa-alias.h
index 59f0ebca953..5b628f2e7cd 100644
--- a/gcc/tree-ssa-alias.h
+++ b/gcc/tree-ssa-alias.h
@@ -108,7 +108,7 @@ extern bool stmt_may_clobber_ref_p (gimple, tree);
 extern bool stmt_may_clobber_ref_p_1 (gimple, ao_ref *);
 extern bool call_may_clobber_ref_p (gimple, tree);
 extern bool stmt_kills_ref_p (gimple, tree);
-extern tree get_continuation_for_phi (gimple, ao_ref *, bitmap *);
+extern tree get_continuation_for_phi (gimple, ao_ref *, bitmap *, bool);
 extern void *walk_non_aliased_vuses (ao_ref *, tree,
 				     void *(*)(ao_ref *, tree, void *),
 				     void *(*)(ao_ref *, tree, void *), void *);
diff --git a/gcc/tree-ssa-loop-im.c b/gcc/tree-ssa-loop-im.c
index 11777deed16..b7494819982 100644
--- a/gcc/tree-ssa-loop-im.c
+++ b/gcc/tree-ssa-loop-im.c
@@ -1480,9 +1480,8 @@ free_mem_ref_locs (mem_ref_locs_p accs)
 /* A function to free the mem_ref object OBJ.  */
 
 static void
-memref_free (void *obj)
+memref_free (struct mem_ref *mem)
 {
-  struct mem_ref *const mem = (struct mem_ref *) obj;
   unsigned i;
   mem_ref_locs_p accs;
 
@@ -1722,8 +1721,7 @@ analyze_memory_references (void)
   unsigned i;
   bitmap empty;
 
-  memory_accesses.refs
-	  = htab_create (100, memref_hash, memref_eq, memref_free);
+  memory_accesses.refs = htab_create (100, memref_hash, memref_eq, NULL);
   memory_accesses.refs_list = NULL;
   memory_accesses.refs_in_loop = VEC_alloc (bitmap, heap,
 					    number_of_loops ());
@@ -2615,6 +2613,7 @@ tree_ssa_lim_finalize (void)
   basic_block bb;
   unsigned i;
   bitmap b;
+  mem_ref_p ref;
 
   free_aux_for_edges ();
 
@@ -2623,9 +2622,12 @@ tree_ssa_lim_finalize (void)
 
   pointer_map_destroy (lim_aux_data_map);
 
-  VEC_free (mem_ref_p, heap, memory_accesses.refs_list);
   htab_delete (memory_accesses.refs);
 
+  FOR_EACH_VEC_ELT (mem_ref_p, memory_accesses.refs_list, i, ref)
+    memref_free (ref);
+  VEC_free (mem_ref_p, heap, memory_accesses.refs_list);
+
   FOR_EACH_VEC_ELT (bitmap, memory_accesses.refs_in_loop, i, b)
     BITMAP_FREE (b);
   VEC_free (bitmap, heap, memory_accesses.refs_in_loop);
@@ -2639,7 +2641,7 @@ tree_ssa_lim_finalize (void)
   VEC_free (bitmap, heap, memory_accesses.all_refs_stored_in_loop);
 
   if (memory_accesses.ttae_cache)
-    pointer_map_destroy (memory_accesses.ttae_cache);
+    free_affine_expand_cache (&memory_accesses.ttae_cache);
 }
 
 /* Moves invariants from loops.  Only "expensive" invariants are moved out --
diff --git a/gcc/tree-ssa-loop-niter.c b/gcc/tree-ssa-loop-niter.c
index 851e8849970..15ea06b8b9b 100644
--- a/gcc/tree-ssa-loop-niter.c
+++ b/gcc/tree-ssa-loop-niter.c
@@ -2290,7 +2290,10 @@ find_loop_niter_by_eval (struct loop *loop, edge *exit)
   /* Loops with multiple exits are expensive to handle and less important.  */
   if (!flag_expensive_optimizations
       && VEC_length (edge, exits) > 1)
-    return chrec_dont_know;
+    {
+      VEC_free (edge, heap, exits);
+      return chrec_dont_know;
+    }
 
   FOR_EACH_VEC_ELT (edge, exits, i, ex)
     {
diff --git a/gcc/tree-ssa-pre.c b/gcc/tree-ssa-pre.c
index 0289407db21..8e7f2550ef3 100644
--- a/gcc/tree-ssa-pre.c
+++ b/gcc/tree-ssa-pre.c
@@ -1283,7 +1283,7 @@ translate_vuse_through_block (VEC (vn_reference_op_s, heap) *operands,
 	  bitmap visited = NULL;
 	  /* Try to find a vuse that dominates this phi node by skipping
 	     non-clobbering statements.  */
-	  vuse = get_continuation_for_phi (phi, &ref, &visited);
+	  vuse = get_continuation_for_phi (phi, &ref, &visited, false);
 	  if (visited)
 	    BITMAP_FREE (visited);
 	}
diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c
index 8c0dbf736c6..f7a0b53e8e0 100644
--- a/gcc/tree-ssa-sccvn.c
+++ b/gcc/tree-ssa-sccvn.c
@@ -3590,6 +3590,8 @@ extract_and_process_scc_for_name (tree name)
 	fprintf (dump_file, "WARNING: Giving up with SCCVN due to "
 		 "SCC size %u exceeding %u\n", VEC_length (tree, scc),
 		 (unsigned)PARAM_VALUE (PARAM_SCCVN_MAX_SCC_SIZE));
+
+      VEC_free (tree, heap, scc);
       return false;
     }
 
diff --git a/gcc/tree-ssa-structalias.c b/gcc/tree-ssa-structalias.c
index b65f5aac02c..f8532f59a45 100644
--- a/gcc/tree-ssa-structalias.c
+++ b/gcc/tree-ssa-structalias.c
@@ -3735,29 +3735,43 @@ handle_rhs_call (gimple stmt, VEC(ce_s, heap) **results)
       /* As we compute ESCAPED context-insensitive we do not gain
          any precision with just EAF_NOCLOBBER but not EAF_NOESCAPE
 	 set.  The argument would still get clobbered through the
-	 escape solution.
-	 ???  We might get away with less (and more precise) constraints
-	 if using a temporary for transitively closing things.  */
+	 escape solution.  */
       if ((flags & EAF_NOCLOBBER)
 	   && (flags & EAF_NOESCAPE))
 	{
 	  varinfo_t uses = get_call_use_vi (stmt);
 	  if (!(flags & EAF_DIRECT))
-	    make_transitive_closure_constraints (uses);
-	  make_constraint_to (uses->id, arg);
+	    {
+	      varinfo_t tem = new_var_info (NULL_TREE, "callarg");
+	      make_constraint_to (tem->id, arg);
+	      make_transitive_closure_constraints (tem);
+	      make_copy_constraint (uses, tem->id);
+	    }
+	  else
+	    make_constraint_to (uses->id, arg);
 	  returns_uses = true;
 	}
       else if (flags & EAF_NOESCAPE)
 	{
+	  struct constraint_expr lhs, rhs;
 	  varinfo_t uses = get_call_use_vi (stmt);
 	  varinfo_t clobbers = get_call_clobber_vi (stmt);
+	  varinfo_t tem = new_var_info (NULL_TREE, "callarg");
+	  make_constraint_to (tem->id, arg);
 	  if (!(flags & EAF_DIRECT))
-	    {
-	      make_transitive_closure_constraints (uses);
-	      make_transitive_closure_constraints (clobbers);
-	    }
-	  make_constraint_to (uses->id, arg);
-	  make_constraint_to (clobbers->id, arg);
+	    make_transitive_closure_constraints (tem);
+	  make_copy_constraint (uses, tem->id);
+	  make_copy_constraint (clobbers, tem->id);
+	  /* Add *tem = nonlocal, do not add *tem = callused as
+	     EAF_NOESCAPE parameters do not escape to other parameters
+	     and all other uses appear in NONLOCAL as well.  */
+	  lhs.type = DEREF;
+	  lhs.var = tem->id;
+	  lhs.offset = 0;
+	  rhs.type = SCALAR;
+	  rhs.var = nonlocal_id;
+	  rhs.offset = 0;
+	  process_constraint (new_constraint (lhs, rhs));
 	  returns_uses = true;
 	}
       else
@@ -3859,9 +3873,11 @@ handle_lhs_call (gimple stmt, tree lhs, int flags, VEC(ce_s, heap) *rhsc,
       tmpc.offset = 0;
       tmpc.type = ADDRESSOF;
       VEC_safe_push (ce_s, heap, rhsc, &tmpc);
+      process_all_all_constraints (lhsc, rhsc);
+      VEC_free (ce_s, heap, rhsc);
     }
-
-  process_all_all_constraints (lhsc, rhsc);
+  else
+    process_all_all_constraints (lhsc, rhsc);
 
   VEC_free (ce_s, heap, lhsc);
 }
diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c
index 24763f7c5c3..bd3945801bc 100644
--- a/gcc/tree-vect-slp.c
+++ b/gcc/tree-vect-slp.c
@@ -95,6 +95,7 @@ vect_free_slp_instance (slp_instance instance)
   vect_free_slp_tree (SLP_INSTANCE_TREE (instance));
   VEC_free (int, heap, SLP_INSTANCE_LOAD_PERMUTATION (instance));
   VEC_free (slp_tree, heap, SLP_INSTANCE_LOADS (instance));
+  free (instance);
 }
 
 
@@ -1569,6 +1570,9 @@ vect_analyze_slp_instance (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo,
           if (vect_print_dump_info (REPORT_SLP))
             fprintf (vect_dump, "Build SLP failed: unrolling required in basic"
                                " block SLP");
+	  vect_free_slp_tree (node);
+	  VEC_free (int, heap, load_permutation);
+	  VEC_free (slp_tree, heap, loads);
           return false;
         }
 
@@ -1825,8 +1829,11 @@ new_bb_vec_info (basic_block bb)
 static void
 destroy_bb_vec_info (bb_vec_info bb_vinfo)
 {
+  VEC (slp_instance, heap) *slp_instances;
+  slp_instance instance;
   basic_block bb;
   gimple_stmt_iterator si;
+  unsigned i;
 
   if (!bb_vinfo)
     return;
@@ -1846,6 +1853,9 @@ destroy_bb_vec_info (bb_vec_info bb_vinfo)
   free_data_refs (BB_VINFO_DATAREFS (bb_vinfo));
   free_dependence_relations (BB_VINFO_DDRS (bb_vinfo));
   VEC_free (gimple, heap, BB_VINFO_STRIDED_STORES (bb_vinfo));
+  slp_instances = BB_VINFO_SLP_INSTANCES (bb_vinfo);
+  FOR_EACH_VEC_ELT (slp_instance, slp_instances, i, instance)
+    vect_free_slp_instance (instance);
   VEC_free (slp_instance, heap, BB_VINFO_SLP_INSTANCES (bb_vinfo));
   free (bb_vinfo);
   bb->aux = NULL;
diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c
index f33e1e233c3..20690e67961 100644
--- a/gcc/tree-vect-stmts.c
+++ b/gcc/tree-vect-stmts.c
@@ -3527,22 +3527,6 @@ vectorizable_operation (gimple stmt, gimple_stmt_iterator *gsi,
   /* Handle def.  */
   vec_dest = vect_create_destination_var (scalar_dest, vectype);
 
-  /* Allocate VECs for vector operands.  In case of SLP, vector operands are
-     created in the previous stages of the recursion, so no allocation is
-     needed, except for the case of shift with scalar shift argument.  In that
-     case we store the scalar operand in VEC_OPRNDS1 for every vector stmt to
-     be created to vectorize the SLP group, i.e., SLP_NODE->VEC_STMTS_SIZE.
-     In case of loop-based vectorization we allocate VECs of size 1.  We
-     allocate VEC_OPRNDS1 only in case of binary operation.  */
-  if (!slp_node)
-    {
-      vec_oprnds0 = VEC_alloc (tree, heap, 1);
-      if (op_type == binary_op || op_type == ternary_op)
-        vec_oprnds1 = VEC_alloc (tree, heap, 1);
-      if (op_type == ternary_op)
-        vec_oprnds2 = VEC_alloc (tree, heap, 1);
-    }
-
   /* In case the vectorization factor (VF) is bigger than the number
      of elements that we can fit in a vectype (nunits), we have to generate
      more than one vector stmt - i.e - we need to "unroll" the
@@ -5715,7 +5699,7 @@ new_stmt_vec_info (gimple stmt, loop_vec_info loop_vinfo,
   else
     STMT_VINFO_DEF_TYPE (res) = vect_internal_def;
 
-  STMT_VINFO_SAME_ALIGN_REFS (res) = VEC_alloc (dr_p, heap, 5);
+  STMT_VINFO_SAME_ALIGN_REFS (res) = NULL;
   STMT_VINFO_INSIDE_OF_LOOP_COST (res) = 0;
   STMT_VINFO_OUTSIDE_OF_LOOP_COST (res) = 0;
   STMT_SLP_TYPE (res) = loop_vect;
diff --git a/gcc/tree-vrp.c b/gcc/tree-vrp.c
index 3f5ec664be3..43f661cffca 100644
--- a/gcc/tree-vrp.c
+++ b/gcc/tree-vrp.c
@@ -1316,41 +1316,25 @@ compare_values (tree val1, tree val2)
 }
 
 
-/* Return 1 if VAL is inside value range VR (VR->MIN <= VAL <= VR->MAX),
-          0 if VAL is not inside VR,
+/* Return 1 if VAL is inside value range MIN <= VAL <= MAX,
+          0 if VAL is not inside [MIN, MAX],
 	 -2 if we cannot tell either way.
 
-   FIXME, the current semantics of this functions are a bit quirky
-	  when taken in the context of VRP.  In here we do not care
-	  about VR's type.  If VR is the anti-range ~[3, 5] the call
-	  value_inside_range (4, VR) will return 1.
-
-	  This is counter-intuitive in a strict sense, but the callers
-	  currently expect this.  They are calling the function
-	  merely to determine whether VR->MIN <= VAL <= VR->MAX.  The
-	  callers are applying the VR_RANGE/VR_ANTI_RANGE semantics
-	  themselves.
-
-	  This also applies to value_ranges_intersect_p and
-	  range_includes_zero_p.  The semantics of VR_RANGE and
-	  VR_ANTI_RANGE should be encoded here, but that also means
-	  adapting the users of these functions to the new semantics.
-
    Benchmark compile/20001226-1.c compilation time after changing this
    function.  */
 
 static inline int
-value_inside_range (tree val, value_range_t * vr)
+value_inside_range (tree val, tree min, tree max)
 {
   int cmp1, cmp2;
 
-  cmp1 = operand_less_p (val, vr->min);
+  cmp1 = operand_less_p (val, min);
   if (cmp1 == -2)
     return -2;
   if (cmp1 == 1)
     return 0;
 
-  cmp2 = operand_less_p (vr->max, val);
+  cmp2 = operand_less_p (max, val);
   if (cmp2 == -2)
     return -2;
 
@@ -1379,23 +1363,14 @@ value_ranges_intersect_p (value_range_t *vr0, value_range_t *vr1)
 }
 
 
-/* Return true if VR includes the value zero, false otherwise.  FIXME,
-   currently this will return false for an anti-range like ~[-4, 3].
-   This will be wrong when the semantics of value_inside_range are
-   modified (currently the users of this function expect these
-   semantics).  */
+/* Return 1 if [MIN, MAX] includes the value zero, 0 if it does not
+   include the value zero, -2 if we cannot tell.  */
 
-static inline bool
-range_includes_zero_p (value_range_t *vr)
+static inline int
+range_includes_zero_p (tree min, tree max)
 {
-  tree zero;
-
-  gcc_assert (vr->type != VR_UNDEFINED
-              && vr->type != VR_VARYING
-	      && !symbolic_range_p (vr));
-
-  zero = build_int_cst (TREE_TYPE (vr->min), 0);
-  return (value_inside_range (zero, vr) == 1);
+  tree zero = build_int_cst (TREE_TYPE (min), 0);
+  return value_inside_range (zero, min, max);
 }
 
 /* Return true if *VR is know to only contain nonnegative values.  */
@@ -2609,7 +2584,7 @@ extract_range_from_binary_expr_1 (value_range_t *vr,
 	     gives [min / 4, max / 4] range.  */
 	  if (vr1.type == VR_RANGE
 	      && !symbolic_range_p (&vr1)
-	      && !range_includes_zero_p (&vr1))
+	      && range_includes_zero_p (vr1.min, vr1.max) == 0)
 	    {
 	      vr0.type = type = VR_RANGE;
 	      vr0.min = vrp_val_min (expr_type);
@@ -2626,8 +2601,7 @@ extract_range_from_binary_expr_1 (value_range_t *vr,
 	 not eliminate a division by zero.  */
       if (cfun->can_throw_non_call_exceptions
 	  && (vr1.type != VR_RANGE
-	      || symbolic_range_p (&vr1)
-	      || range_includes_zero_p (&vr1)))
+	      || range_includes_zero_p (vr1.min, vr1.max) != 0))
 	{
 	  set_value_range_to_varying (vr);
 	  return;
@@ -2638,8 +2612,7 @@ extract_range_from_binary_expr_1 (value_range_t *vr,
 	 include 0.  */
       if (vr0.type == VR_RANGE
 	  && (vr1.type != VR_RANGE
-	      || symbolic_range_p (&vr1)
-	      || range_includes_zero_p (&vr1)))
+	      || range_includes_zero_p (vr1.min, vr1.max) != 0))
 	{
 	  tree zero = build_int_cst (TREE_TYPE (vr0.min), 0);
 	  int cmp;
@@ -2691,8 +2664,7 @@ extract_range_from_binary_expr_1 (value_range_t *vr,
   else if (code == TRUNC_MOD_EXPR)
     {
       if (vr1.type != VR_RANGE
-	  || symbolic_range_p (&vr1)
-	  || range_includes_zero_p (&vr1)
+	  || range_includes_zero_p (vr1.min, vr1.max) != 0
 	  || vrp_val_is_min (vr1.min))
 	{
 	  set_value_range_to_varying (vr);
@@ -3093,7 +3065,7 @@ extract_range_from_unary_expr_1 (value_range_t *vr,
 	 ~[-INF, min(MIN, MAX)].  */
       if (vr0.type == VR_ANTI_RANGE)
 	{
-	  if (range_includes_zero_p (&vr0))
+	  if (range_includes_zero_p (vr0.min, vr0.max) == 1)
 	    {
 	      /* Take the lower of the two values.  */
 	      if (cmp != 1)
@@ -3144,7 +3116,7 @@ extract_range_from_unary_expr_1 (value_range_t *vr,
 
       /* If the range contains zero then we know that the minimum value in the
          range will be zero.  */
-      else if (range_includes_zero_p (&vr0))
+      else if (range_includes_zero_p (vr0.min, vr0.max) == 1)
 	{
 	  if (cmp == 1)
 	    max = min;
@@ -3759,7 +3731,7 @@ compare_range_with_value (enum tree_code comp, value_range_t *vr, tree val,
 	return NULL_TREE;
 
       /* ~[VAL_1, VAL_2] OP VAL is known if VAL_1 <= VAL <= VAL_2.  */
-      if (value_inside_range (val, vr) == 1)
+      if (value_inside_range (val, vr->min, vr->max) == 1)
 	return (comp == NE_EXPR) ? boolean_true_node : boolean_false_node;
 
       return NULL_TREE;
@@ -6570,11 +6542,15 @@ give_up:
      anti-ranges from ranges is necessary because of the odd
      semantics of range_includes_zero_p and friends.  */
   if (!symbolic_range_p (vr0)
-      && ((vr0->type == VR_RANGE && !range_includes_zero_p (vr0))
-	  || (vr0->type == VR_ANTI_RANGE && range_includes_zero_p (vr0)))
+      && ((vr0->type == VR_RANGE
+	   && range_includes_zero_p (vr0->min, vr0->max) == 0)
+	  || (vr0->type == VR_ANTI_RANGE
+	      && range_includes_zero_p (vr0->min, vr0->max) == 1))
       && !symbolic_range_p (vr1)
-      && ((vr1->type == VR_RANGE && !range_includes_zero_p (vr1))
-	  || (vr1->type == VR_ANTI_RANGE && range_includes_zero_p (vr1))))
+      && ((vr1->type == VR_RANGE
+	   && range_includes_zero_p (vr1->min, vr1->max) == 0)
+	  || (vr1->type == VR_ANTI_RANGE
+	      && range_includes_zero_p (vr1->min, vr1->max) == 1)))
     {
       set_value_range_to_nonnull (vr0, TREE_TYPE (vr0->min));
 
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 2280ec564fc..e0b52e153f0 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,28 @@
+2012-09-05  Georg-Johann Lay  <avr@gjlay.de>
+
+	Backport from 2012-09-05 mainline r190697.
+	
+	PR target/54461
+	* config.host (tmake_file,host=avr-*-*): Add avr/t-avrlibc if
+	configured --with-avrlibc.
+	* config/avr/t-avrlibc: New file.
+	* Makefile.in (FPBIT_FUNCS): filter-out LIB2FUNCS_EXCLUDE.
+	(DPBIT_FUNCS): Ditto.
+	(TPBIT_FUNCS): Ditto.
+
+2012-08-21  Ian Lance Taylor  <iant@google.com>
+
+	* config/i386/morestack.S (__morestack_non_split): Increase amount
+	of space allocated for non-split code stack.
+
+2012-08-16  David Edelsohn  <dje.gcc@gmail.com>
+
+	Backported from mainline
+	2012-08-16  David Edelsohn  <dje.gcc@gmail.com>
+
+	* config.host (*-*-aix*): Move rs6000/t-ibm-ldouble after
+	rs6000/t-slibgcc-aix.
+
 2012-06-14  Release Manager
 
 	* GCC 4.7.1 released.
diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in
index bcd92848b96..f38d5b4a250 100644
--- a/libgcc/Makefile.in
+++ b/libgcc/Makefile.in
@@ -517,6 +517,10 @@ FPBIT_FUNCS := $(filter-out _sf_to_tf,$(FPBIT_FUNCS))
 DPBIT_FUNCS := $(filter-out _df_to_tf,$(DPBIT_FUNCS))
 endif
 
+FPBIT_FUNCS := $(filter-out $(LIB2FUNCS_EXCLUDE),$(FPBIT_FUNCS))
+DPBIT_FUNCS := $(filter-out $(LIB2FUNCS_EXCLUDE),$(DPBIT_FUNCS))
+TPBIT_FUNCS := $(filter-out $(LIB2FUNCS_EXCLUDE),$(TPBIT_FUNCS))
+
 fpbit-src := $(srcdir)/fp-bit.c
 
 # Build FPBIT.
diff --git a/libgcc/config.host b/libgcc/config.host
index d41ef6432ba..ef9791bffd6 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -391,6 +391,9 @@ avr-*-rtems*)
 avr-*-*)
 	# Make HImode functions for AVR
 	tmake_file="${cpu_type}/t-avr t-fpbit"
+	if test x${with_avrlibc} = xyes; then
+	    tmake_file="$tmake_file ${cpu_type}/t-avrlibc"
+	fi
 	tm_file="$tm_file avr/avr-lib.h"
 	;;
 bfin*-elf*)
@@ -916,15 +919,15 @@ powerpcle-*-eabi*)
 	;;
 rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
 	md_unwind_header=rs6000/aix-unwind.h
-	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-ibm-ldouble rs6000/t-slibgcc-aix"
+	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
 	;;
 rs6000-ibm-aix5.1.* | powerpc-ibm-aix5.1.*)
 	md_unwind_header=rs6000/aix-unwind.h
-	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-ibm-ldouble rs6000/t-slibgcc-aix"
+	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
 	;;
 rs6000-ibm-aix[56789].* | powerpc-ibm-aix[56789].*)
 	md_unwind_header=rs6000/aix-unwind.h
-	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-ibm-ldouble rs6000/t-slibgcc-aix"
+	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
 	;;
 rl78-*-elf)
 	tmake_file="$tm_file t-fdpbit rl78/t-rl78"
diff --git a/libgcc/config/avr/t-avrlibc b/libgcc/config/avr/t-avrlibc
new file mode 100644
index 00000000000..543cdf6d89f
--- /dev/null
+++ b/libgcc/config/avr/t-avrlibc
@@ -0,0 +1,66 @@
+# This file is used with --with-avrlibc=yes
+#
+# AVR-Libc comes with hand-optimized float routines.
+# For historical reasons, these routines live in AVR-Libc
+# and not in libgcc and use the same function names like libgcc.
+# To get the best support, i.e. always use the routines from
+# AVR-Libc, we remove these routines from libgcc.
+#
+# See also PR54461.
+#
+#
+# Arithmetic:
+#     __addsf3 __subsf3 __divsf3 __mulsf3 __negsf2
+#
+# Comparison:
+#     __cmpsf2 __unordsf2
+#     __eqsf2 __lesf2 __ltsf2 __nesf2 __gesf2 __gtsf2
+#
+# Conversion:
+#     __fixsfdi __fixunssfdi __floatdisf __floatundisf
+#     __fixsfsi __fixunssfsi __floatsisf __floatunsisf
+#
+#
+# These functions are contained in modules:
+#
+# _addsub_sf.o:   __addsf3  __subsf3
+# _mul_sf.o:      __mulsf3
+# _div_sf.o:      __divsf3
+# _negate_sf.o:   __negsf2
+#
+# _compare_sf.o:  __cmpsf2
+# _unord_sf.o:    __unordsf2
+# _eq_sf.o:       __eqsf2
+# _ne_sf.o:       __nesf2
+# _ge_sf.o:       __gesf2
+# _gt_sf.o:       __gtsf2
+# _le_sf.o:       __lesf2
+# _lt_sf.o:       __ltsf2
+#
+# _fixsfdi.o:     __fixsfdi
+# _fixunssfdi.o:  __fixunssfdi
+# _fixunssfsi.o:  __fixunssfsi
+# _floatdisf.o:   __floatdisf
+# _floatundisf.o: __floatundisf
+# _sf_to_si.o:    __fixsfsi
+# _si_to_sf.o:    __floatsisf
+# _usi_to_sf.o:   __floatunsisf
+
+
+# SFmode
+LIB2FUNCS_EXCLUDE += \
+	_addsub_sf \
+	_negate_sf \
+	_mul_sf _div_sf \
+	\
+	_compare_sf \
+	_unord_sf \
+	_eq_sf _ne_sf \
+	_gt_sf _ge_sf \
+	_lt_sf _le_sf \
+	\
+	_si_to_sf  _sf_to_si \
+	_usi_to_sf _sf_to_usi \
+	_fixunssfsi _fixsfdi \
+	_fixunssfdi \
+	_floatdisf _floatundisf
diff --git a/libgcc/config/i386/morestack.S b/libgcc/config/i386/morestack.S
index 228d6901abd..9528431f7e6 100644
--- a/libgcc/config/i386/morestack.S
+++ b/libgcc/config/i386/morestack.S
@@ -83,6 +83,9 @@
 #endif
 
 
+# The amount of space we ask for when calling non-split-stack code.
+#define NON_SPLIT_STACK 0x100000
+
 # This entry point is for split-stack code which calls non-split-stack
 # code.  When the linker sees this case, it converts the call to
 # __morestack to call __morestack_non_split instead.  We just bump the
@@ -109,7 +112,7 @@ __morestack_non_split:
 
 	movl	%esp,%eax		# Current stack,
 	subl	8(%esp),%eax		# less required stack frame size,
-	subl	$0x4000,%eax		# less space for non-split code.
+	subl	$NON_SPLIT_STACK,%eax	# less space for non-split code.
 	cmpl	%gs:0x30,%eax		# See if we have enough space.
 	jb	2f			# Get more space if we need it.
 
@@ -171,7 +174,8 @@ __morestack_non_split:
 
 	.cfi_adjust_cfa_offset -4	# Account for popped register.
 
-	addl	$0x5000+BACKOFF,4(%esp)	# Increment space we request.
+	# Increment space we request.
+	addl	$NON_SPLIT_STACK+0x1000+BACKOFF,4(%esp)
 
 	# Fall through into morestack.
 
@@ -186,7 +190,7 @@ __morestack_non_split:
 
 	movq	%rsp,%rax		# Current stack,
 	subq	%r10,%rax		# less required stack frame size,
-	subq	$0x4000,%rax		# less space for non-split code.
+	subq	$NON_SPLIT_STACK,%rax	# less space for non-split code.
 
 #ifdef __LP64__
 	cmpq	%fs:0x70,%rax		# See if we have enough space.
@@ -219,7 +223,8 @@ __morestack_non_split:
 
 	.cfi_adjust_cfa_offset -8	# Adjust for popped register.
 
-	addq	$0x5000+BACKOFF,%r10	# Increment space we request.
+	# Increment space we request.
+	addq	$NON_SPLIT_STACK+0x1000+BACKOFF,%r10
 
 	# Fall through into morestack.
 
diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index f1646f5ca15..b7bfd7222a1 100644
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,7 @@
+2012-09-05  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/fpu-387.h (set_fpu): Prefix stmxcsr and ldmxcsr with %v.
+
 2012-06-14  Release Manager
 
 	* GCC 4.7.1 released.
diff --git a/libgfortran/config/fpu-387.h b/libgfortran/config/fpu-387.h
index 8bf55b28a61..d2b7a05094f 100644
--- a/libgfortran/config/fpu-387.h
+++ b/libgfortran/config/fpu-387.h
@@ -118,7 +118,7 @@ void set_fpu (void)
     {
       unsigned int cw_sse;
 
-      asm volatile ("stmxcsr %0" : "=m" (cw_sse));
+      asm volatile ("%vstmxcsr %0" : "=m" (cw_sse));
 
       cw_sse &= 0xffff0000;
       cw_sse |= (_FPU_MASK_IM | _FPU_MASK_DM | _FPU_MASK_ZM | _FPU_MASK_OM
@@ -131,6 +131,6 @@ void set_fpu (void)
       if (options.fpe & GFC_FPE_UNDERFLOW) cw_sse &= ~(_FPU_MASK_UM << 7);
       if (options.fpe & GFC_FPE_INEXACT) cw_sse &= ~(_FPU_MASK_PM << 7);
 
-      asm volatile ("ldmxcsr %0" : : "m" (cw_sse));
+      asm volatile ("%vldmxcsr %0" : : "m" (cw_sse));
     }
 }
diff --git a/libgo/go/debug/dwarf/line.go b/libgo/go/debug/dwarf/line.go
index f3456fba0a4..3ab2f2b30cb 100644
--- a/libgo/go/debug/dwarf/line.go
+++ b/libgo/go/debug/dwarf/line.go
@@ -67,12 +67,22 @@ func (d *Data) readUnitLine(i int, u *unit) error {
 		switch e.Tag {
 		case TagCompileUnit, TagSubprogram, TagEntryPoint, TagInlinedSubroutine:
 			low, lowok := e.Val(AttrLowpc).(uint64)
-			high, highok := e.Val(AttrHighpc).(uint64)
+			var high uint64
+			var highok bool
+			switch v := e.Val(AttrHighpc).(type) {
+			case uint64:
+				high = v
+				highok = true
+			case int64:
+				high = low + uint64(v)
+				highok = true
+			}
 			if lowok && highok {
 				u.pc = append(u.pc, addrRange{low, high})
-			} else if f, ok := e.Val(AttrRanges).(Offset); ok {
-				// TODO: Handle AttrRanges and .debug_ranges.
-				_ = f
+			} else if off, ok := e.Val(AttrRanges).(Offset); ok {
+				if err := d.readAddressRanges(off, low, u); err != nil {
+					return err
+				}
 			}
 			val := e.Val(AttrStmtList)
 			if val != nil {
@@ -98,6 +108,38 @@ func (d *Data) readUnitLine(i int, u *unit) error {
 	return nil
 }
 
+// readAddressRanges adds address ranges to a unit.
+func (d *Data) readAddressRanges(off Offset, base uint64, u *unit) error {
+	b := makeBuf(d, u, "ranges", off, d.ranges[off:])
+	var highest uint64
+	switch u.addrsize {
+	case 1:
+		highest = 0xff
+	case 2:
+		highest = 0xffff
+	case 4:
+		highest = 0xffffffff
+	case 8:
+		highest = 0xffffffffffffffff
+	default:
+		return errors.New("unknown address size")
+	}
+	for {
+		if b.err != nil {
+			return b.err
+		}
+		low := b.addr()
+		high := b.addr()
+		if low == 0 && high == 0 {
+			return b.err
+		} else if low == highest {
+			base = high
+		} else {
+			u.pc = append(u.pc, addrRange{low + base, high + base})
+		}
+	}
+}
+
 // findLine finds the line information for a PC value, given the unit
 // containing the information.
 func (d *Data) findLine(u *unit, pc uint64) ([]*Line, error) {
diff --git a/libgo/go/debug/elf/file.go b/libgo/go/debug/elf/file.go
index c2c03d2c647..31895f192c5 100644
--- a/libgo/go/debug/elf/file.go
+++ b/libgo/go/debug/elf/file.go
@@ -563,7 +563,7 @@ func (f *File) DWARF() (*dwarf.Data, error) {
 	// There are many other DWARF sections, but these
 	// are the required ones, and the debug/dwarf package
 	// does not use the others, so don't bother loading them.
-	var names = [...]string{"abbrev", "info", "line", "str"}
+	var names = [...]string{"abbrev", "info", "line", "ranges", "str"}
 	var dat [len(names)][]byte
 	for i, name := range names {
 		name = ".debug_" + name
@@ -592,8 +592,8 @@ func (f *File) DWARF() (*dwarf.Data, error) {
 		}
 	}
 
-	abbrev, info, line, str := dat[0], dat[1], dat[2], dat[3]
-	return dwarf.New(abbrev, nil, nil, info, line, nil, nil, str)
+	abbrev, info, line, ranges, str := dat[0], dat[1], dat[2], dat[3], dat[4]
+	return dwarf.New(abbrev, nil, nil, info, line, nil, ranges, str)
 }
 
 // Symbols returns the symbol table for f.
diff --git a/libgo/go/os/dir.go b/libgo/go/os/dir.go
index 02b21e6f7da..c77560fc08c 100644
--- a/libgo/go/os/dir.go
+++ b/libgo/go/os/dir.go
@@ -49,7 +49,7 @@ func (file *File) readdirnames(n int) (names []string, err error) {
 		file.dirinfo.dir = r
 	}
 
-	entry_dirent := unsafe.Pointer(&file.dirinfo.buf[0]).(*syscall.Dirent)
+	entry_dirent := (*syscall.Dirent)(unsafe.Pointer(&file.dirinfo.buf[0]))
 
 	size := n
 	if size < 0 {
diff --git a/libgo/mksysinfo.sh b/libgo/mksysinfo.sh
index 39553445d07..315d60cc39d 100755
--- a/libgo/mksysinfo.sh
+++ b/libgo/mksysinfo.sh
@@ -211,6 +211,16 @@ if ! grep '^const O_CLOEXEC' ${OUT} >/dev/null 2>&1; then
   echo "const O_CLOEXEC = 0" >> ${OUT}
 fi
 
+# These flags can be lost on i386 GNU/Linux when using
+# -D_FILE_OFFSET_BITS=64, because we see "#define F_SETLK F_SETLK64"
+# before we see the definition of F_SETLK64.
+for flag in F_GETLK F_SETLK F_SETLKW; do
+  if ! grep "^const ${flag} " ${OUT} >/dev/null 2>&1 \
+      && grep "^const ${flag}64 " ${OUT} >/dev/null 2>&1; then
+    echo "const ${flag} = ${flag}64" >> ${OUT}
+  fi
+done
+
 # The signal numbers.
 grep '^const _SIG[^_]' gen-sysinfo.go | \
   grep -v '^const _SIGEV_' | \
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 7811ee6963d..cb4aa528d86 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,120 @@
+2012-09-09  Jonathan Wakely  <jwakely.gcc@gmail.com>
+
+	PR libstdc++/54388
+	* include/std/array (array::at() const): Ensure lvalue result.
+	* testsuite/23_containers/array/element_access/54388.cc: New.
+
+2012-09-06  Marc Glisse  <marc.glisse@inria.fr>
+	    Paolo Carlini  <paolo.carlini@oracle.com>
+
+	PR libstdc++/54376
+	* include/bits/random.h (lognormal_distribution<>::operator==,
+	gamma_distribution<>::operator==,
+	chi_squared_distribution<>::operator==,
+	fisher_f_distribution<>::operator==,
+	student_t_distribution<>::operator==,
+	binomial_distribution<>::operator==,
+	negative_binomial_distribution<>::operator==,
+	poisson_distribution<>::operator==): Change inline friend definition
+	to non-template.
+	* testsuite/26_numerics/random/binomial_distribution/requirements/
+	explicit_instantiation/1.cc: New.
+	* testsuite/26_numerics/random/cauchy_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/chi_squared_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/discrete_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/exponential_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/extreme_value_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/fisher_f_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/gamma_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/geometric_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/lognormal_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/negative_binomial_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/normal_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/piecewise_constant_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/piecewise_linear_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/poisson_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/student_t_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/uniform_int_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/uniform_real_distribution/
+	requirements/explicit_instantiation/1.cc: Likewise.
+	* testsuite/26_numerics/random/weibull_distribution/requirements/
+	explicit_instantiation/1.cc: Likewise.
+
+2012-08-26  Jonathan Wakely  <jwakely.gcc@gmail.com>
+
+	* testsuite/30_threads/async/54297.cc: Add dg-require-nanosleep.
+
+2012-08-26  Jonathan Wakely  <jwakely.gcc@gmail.com>
+
+	PR libstdc++/54297
+	* src/c++11/future.cc (~_Async_state_common): Move to...
+	* src/c++11/compatibility-thread-c++0x.cc (~_Async_state_common):
+	Here.
+	(_GLIBCXX_ABI_COMPAT_ASYNC): Rename to _GLIBCXX_ASYNC_ABI_COMPAT.
+	* include/std/future (_GLIBCXX_ABI_COMPAT_ASYNC): Likewise.
+
+2012-08-26  Jonathan Wakely  <jwakely.gcc@gmail.com>
+	    Geoff Romer  <gromer@google.com>
+
+	PR libstdc++/54351
+	* include/bits/unique_ptr.h (unique_ptr<T>::~unique_ptr): Do not use
+	reset().
+	(unique_ptr<T[]>::~unique_ptr()): Likewise.
+	* testsuite/20_util/unique_ptr/54351.cc: New.
+	* testsuite/20_util/unique_ptr/assign/48635_neg.cc: Adjust dg-error
+	line numbers.
+
+2012-08-25  Jonathan Wakely  <jwakely.gcc@gmail.com>
+
+	PR libstdc++/54297
+	* include/std/future (~_Async_state_impl): Join thread before
+	derived class members are destroyed.
+	(~_Async_state_common): Only define non-trivial destructor when
+	included from future.cc for ABI compatibility reasons.
+	* src/c++11/future.cc (_GLIBCXX_ABI_COMPAT_ASYNC): Define.
+	* testsuite/30_threads/async/54297.cc: New.
+
+2012-08-13  David Adler  <d.adler.s@gmail.com>
+
+	PR libstdc++/54185
+	* src/c++11/condition_variable.cc (condition_variable): Always
+	destroy native type in destructor.
+	* testsuite/30_threads/condition_variable/54185.cc: New.
+
+2012-08-06  Peter Bergner  <bergner@vnet.ibm.com>
+
+	PR libstdc++/54036
+	* include/decimal/decimal.h (_DEFINE_DECIMAL_UNARY_OP): Use _Op as
+	a unary operator.
+	* testsuite/decimal/pr54036-1.cc: New test.
+	* testsuite/decimal/pr54036-2.cc: Likewise.
+	* testsuite/decimal/pr54036-3.cc: Likewise.
+
+2012-08-02  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r186389:
+	2012-04-12  Andreas Schwab  <schwab@linux-m68k.org>
+
+	* testsuite/Makefile.am (check_DEJAGNUnormal0): Run
+	prettyprinters.exp.
+	* testsuite/Makefile.in: Regenerated.
+
 2012-07-29  François Dumont  <fdumont@gcc.gnu.org>
 
 	PR libstdc++/54075
diff --git a/libstdc++-v3/include/bits/random.h b/libstdc++-v3/include/bits/random.h
index 8f6bf4f7bd5..aa4ce3e8209 100644
--- a/libstdc++-v3/include/bits/random.h
+++ b/libstdc++-v3/include/bits/random.h
@@ -2274,12 +2274,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        the same parameters and the sequences that would
        *        be generated are equal.
        */
-      template<typename _RealType1>
-        friend bool
-        operator==(const std::lognormal_distribution<_RealType1>& __d1,
-		   const std::lognormal_distribution<_RealType1>& __d2)
-        { return (__d1.param() == __d2.param()
-		  && __d1._M_nd == __d2._M_nd); }
+      friend bool
+      operator==(const lognormal_distribution& __d1,
+		 const lognormal_distribution& __d2)
+      { return (__d1.param() == __d2.param()
+		&& __d1._M_nd == __d2._M_nd); }
 
       /**
        * @brief Inserts a %lognormal_distribution random number distribution
@@ -2467,12 +2466,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        parameters and the sequences that would be generated
        *        are equal.
        */
-      template<typename _RealType1>
-        friend bool
-        operator==(const std::gamma_distribution<_RealType1>& __d1,
-		   const std::gamma_distribution<_RealType1>& __d2)
-        { return (__d1.param() == __d2.param()
-		  && __d1._M_nd == __d2._M_nd); }
+      friend bool
+      operator==(const gamma_distribution& __d1,
+		 const gamma_distribution& __d2)
+      { return (__d1.param() == __d2.param()
+		&& __d1._M_nd == __d2._M_nd); }
 
       /**
        * @brief Inserts a %gamma_distribution random number distribution
@@ -2632,11 +2630,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        the same parameters and the sequences that would be
        *        generated are equal.
        */
-      template<typename _RealType1>
-        friend bool
-        operator==(const std::chi_squared_distribution<_RealType1>& __d1,
-		   const std::chi_squared_distribution<_RealType1>& __d2)
-        { return __d1.param() == __d2.param() && __d1._M_gd == __d2._M_gd; }
+      friend bool
+      operator==(const chi_squared_distribution& __d1,
+		 const chi_squared_distribution& __d2)
+      { return __d1.param() == __d2.param() && __d1._M_gd == __d2._M_gd; }
 
       /**
        * @brief Inserts a %chi_squared_distribution random number distribution
@@ -2985,13 +2982,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        the same parameters and the sequences that would
        *        be generated are equal.
        */
-      template<typename _RealType1>
-        friend bool
-        operator==(const std::fisher_f_distribution<_RealType1>& __d1,
-		   const std::fisher_f_distribution<_RealType1>& __d2)
-        { return (__d1.param() == __d2.param()
-		  && __d1._M_gd_x == __d2._M_gd_x
-		  && __d1._M_gd_y == __d2._M_gd_y); }
+      friend bool
+      operator==(const fisher_f_distribution& __d1,
+		 const fisher_f_distribution& __d2)
+      { return (__d1.param() == __d2.param()
+		&& __d1._M_gd_x == __d2._M_gd_x
+		&& __d1._M_gd_y == __d2._M_gd_y); }
 
       /**
        * @brief Inserts a %fisher_f_distribution random number distribution
@@ -3159,12 +3155,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        the same parameters and the sequences that would
        *        be generated are equal.
        */
-      template<typename _RealType1>
-        friend bool
-        operator==(const std::student_t_distribution<_RealType1>& __d1,
-		   const std::student_t_distribution<_RealType1>& __d2)
-        { return (__d1.param() == __d2.param()
-		  && __d1._M_nd == __d2._M_nd && __d1._M_gd == __d2._M_gd); }
+      friend bool
+      operator==(const student_t_distribution& __d1,
+		 const student_t_distribution& __d2)
+      { return (__d1.param() == __d2.param()
+		&& __d1._M_nd == __d2._M_nd && __d1._M_gd == __d2._M_gd); }
 
       /**
        * @brief Inserts a %student_t_distribution random number distribution
@@ -3535,10 +3530,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        the same parameters and the sequences that would
        *        be generated are equal.
        */
-      template<typename _IntType1>
 	friend bool
-        operator==(const std::binomial_distribution<_IntType1>& __d1,
-		   const std::binomial_distribution<_IntType1>& __d2)
+        operator==(const binomial_distribution& __d1,
+		   const binomial_distribution& __d2)
 #ifdef _GLIBCXX_USE_C99_MATH_TR1
 	{ return __d1.param() == __d2.param() && __d1._M_nd == __d2._M_nd; }
 #else
@@ -3892,11 +3886,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
        *        the same parameters and the sequences that would be
        *        generated are equal.
        */
-      template<typename _IntType1>
-        friend bool
-        operator==(const std::negative_binomial_distribution<_IntType1>& __d1,
-		   const std::negative_binomial_distribution<_IntType1>& __d2)
-        { return __d1.param() == __d2.param() && __d1._M_gd == __d2._M_gd; }
+      friend bool
+      operator==(const negative_binomial_distribution& __d1,
+		 const negative_binomial_distribution& __d2)
+      { return __d1.param() == __d2.param() && __d1._M_gd == __d2._M_gd; }
 
       /**
        * @brief Inserts a %negative_binomial_distribution random
@@ -4076,14 +4069,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	*        parameters and the sequences that would be generated
 	*        are equal.
 	*/
-      template<typename _IntType1>
-        friend bool
-        operator==(const std::poisson_distribution<_IntType1>& __d1,
-		   const std::poisson_distribution<_IntType1>& __d2)
+      friend bool
+      operator==(const poisson_distribution& __d1,
+		 const poisson_distribution& __d2)
 #ifdef _GLIBCXX_USE_C99_MATH_TR1
-        { return __d1.param() == __d2.param() && __d1._M_nd == __d2._M_nd; }
+      { return __d1.param() == __d2.param() && __d1._M_nd == __d2._M_nd; }
 #else
-        { return __d1.param() == __d2.param(); }
+      { return __d1.param() == __d2.param(); }
 #endif
 
       /**
diff --git a/libstdc++-v3/include/bits/unique_ptr.h b/libstdc++-v3/include/bits/unique_ptr.h
index 0a127996e52..23937daa29c 100644
--- a/libstdc++-v3/include/bits/unique_ptr.h
+++ b/libstdc++-v3/include/bits/unique_ptr.h
@@ -166,7 +166,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 #endif
 
       // Destructor.
-      ~unique_ptr() noexcept { reset(); }
+      ~unique_ptr() noexcept
+      {
+	auto& __ptr = std::get<0>(_M_t);
+	if (__ptr != nullptr)
+	  get_deleter()(__ptr);
+	__ptr = pointer();
+      }
 
       // Assignment.
       unique_ptr&
@@ -310,7 +316,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	{ }
 
       // Destructor.
-      ~unique_ptr() { reset(); }
+      ~unique_ptr()
+      {
+	auto& __ptr = std::get<0>(_M_t);
+	if (__ptr != nullptr)
+	  get_deleter()(__ptr);
+	__ptr = pointer();
+      }
 
       // Assignment.
       unique_ptr&
diff --git a/libstdc++-v3/include/decimal/decimal.h b/libstdc++-v3/include/decimal/decimal.h
index f8f05734ba8..6bc9e6a9300 100644
--- a/libstdc++-v3/include/decimal/decimal.h
+++ b/libstdc++-v3/include/decimal/decimal.h
@@ -288,7 +288,7 @@ namespace decimal
   inline _Tp operator _Op(_Tp __rhs)		\
   {						\
     _Tp __tmp;					\
-    __tmp.__setval(0 _Op __rhs.__getval());	\
+    __tmp.__setval(_Op __rhs.__getval());	\
     return __tmp;				\
   }
 
diff --git a/libstdc++-v3/include/std/array b/libstdc++-v3/include/std/array
index 8cd53880820..54cb98d7d9a 100644
--- a/libstdc++-v3/include/std/array
+++ b/libstdc++-v3/include/std/array
@@ -164,22 +164,14 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	return _M_instance[__n];
       }
 
-#ifdef __EXCEPTIONS
       constexpr const_reference
       at(size_type __n) const
       {
-	return __n < _Nm ? 
-	       _M_instance[__n] : throw out_of_range(__N("array::at"));
+	// Result of conditional expression must be an lvalue so use
+	// boolean ? lvalue : (throw-expr, lvalue)
+	return __n < _Nm ? _M_instance[__n]
+	  : (std::__throw_out_of_range(__N("array::at")), _M_instance[0]);
       }
-#else
-      const_reference
-      at(size_type __n) const
-      {
-	if (__n >= _Nm)
-	  std::__throw_out_of_range(__N("array::at"));
-	return _M_instance[__n];
-      }
-#endif
 
       reference 
       front()
diff --git a/libstdc++-v3/include/std/future b/libstdc++-v3/include/std/future
index 962400bda65..22fd36a6fce 100644
--- a/libstdc++-v3/include/std/future
+++ b/libstdc++-v3/include/std/future
@@ -1425,10 +1425,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   class __future_base::_Async_state_common : public __future_base::_State_base
   {
   protected:
-#ifdef _GLIBCXX_HAVE_TLS
+#ifdef _GLIBCXX_ASYNC_ABI_COMPAT
     ~_Async_state_common();
 #else
-    ~_Async_state_common() { _M_join(); }
+    ~_Async_state_common() = default;
 #endif
 
     // Allow non-timed waiting functions to block until the thread completes,
@@ -1455,6 +1455,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
         } };
       }
 
+      ~_Async_state_impl() { _M_join(); }
+
     private:
       typedef __future_base::_Ptr<_Result<_Res>> _Ptr_type;
       _Ptr_type _M_result;
diff --git a/libstdc++-v3/src/c++11/compatibility-thread-c++0x.cc b/libstdc++-v3/src/c++11/compatibility-thread-c++0x.cc
index cc8761eea15..e5c7eec419e 100644
--- a/libstdc++-v3/src/c++11/compatibility-thread-c++0x.cc
+++ b/libstdc++-v3/src/c++11/compatibility-thread-c++0x.cc
@@ -22,11 +22,16 @@
 // see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 // <http://www.gnu.org/licenses/>.
 
+#include <bits/c++config.h>
+#if defined(_GLIBCXX_HAVE_TLS) && defined(PIC)
+#define _GLIBCXX_ASYNC_ABI_COMPAT
+#endif
+
 #include <future>
 #include <mutex>
 
 #ifndef __GXX_EXPERIMENTAL_CXX0X__
-# error "compatibility-c++0x.cc must be compiled with -std=gnu++0x"
+# error "compatibility-thread-c++0x.cc must be compiled with -std=gnu++0x"
 #endif
 
 #define _GLIBCXX_ASM_SYMVER(cur, old, version) \
@@ -70,3 +75,23 @@ _GLIBCXX_ASM_SYMVER(_ZN9__gnu_cxx11try_to_lockE, _ZSt11try_to_lock, GLIBCXX_3.4.
 
 #endif
 #endif // _GLIBCXX_HAS_GTHREADS && _GLIBCXX_USE_C99_STDINT_TR1
+
+
+// XXX GLIBCXX_ABI Deprecated
+// gcc-4.7.0
+// <future> export changes
+#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+  && (ATOMIC_INT_LOCK_FREE > 1)
+#if defined(_GLIBCXX_HAVE_TLS) && defined(PIC)
+namespace std _GLIBCXX_VISIBILITY(default)
+{
+_GLIBCXX_BEGIN_NAMESPACE_VERSION
+  __future_base::_Async_state_common::~_Async_state_common() { _M_join(); }
+
+  // Explicit instantiation due to -fno-implicit-instantiation.
+  template void call_once(once_flag&, void (thread::*&&)(), reference_wrapper<thread>&&);
+  template _Bind_simple_helper<void (thread::*)(), reference_wrapper<thread>>::__type __bind_simple(void (thread::*&&)(), reference_wrapper<thread>&&);
+_GLIBCXX_END_NAMESPACE_VERSION
+} // namespace std
+#endif
+#endif // _GLIBCXX_HAS_GTHREADS && _GLIBCXX_USE_C99_STDINT_TR1
diff --git a/libstdc++-v3/src/c++11/condition_variable.cc b/libstdc++-v3/src/c++11/condition_variable.cc
index 9cd07637ecd..4c9aa3e7345 100644
--- a/libstdc++-v3/src/c++11/condition_variable.cc
+++ b/libstdc++-v3/src/c++11/condition_variable.cc
@@ -1,6 +1,6 @@
 // condition_variable -*- C++ -*-
 
-// Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+// Copyright (C) 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
 //
 // This file is part of the GNU ISO C++ Library.  This library is free
 // software; you can redistribute it and/or modify it under the
@@ -32,12 +32,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
 #ifdef __GTHREAD_COND_INIT
   condition_variable::condition_variable() noexcept = default;
-  condition_variable::~condition_variable() noexcept = default;
 #else
   condition_variable::condition_variable() noexcept
   {
     __GTHREAD_COND_INIT_FUNCTION(&_M_cond);
   }
+#endif
 
   condition_variable::~condition_variable() noexcept
   {
@@ -45,7 +45,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
     /* int __e = */ __gthread_cond_destroy(&_M_cond);
     // if __e == EBUSY then blocked
   }
-#endif
 
   void
   condition_variable::wait(unique_lock<mutex>& __lock)
diff --git a/libstdc++-v3/src/c++11/future.cc b/libstdc++-v3/src/c++11/future.cc
index 380c3a45185..05525372618 100644
--- a/libstdc++-v3/src/c++11/future.cc
+++ b/libstdc++-v3/src/c++11/future.cc
@@ -84,14 +84,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __future_base::_Result_base::~_Result_base() = default;
 
   __future_base::_State_base::~_State_base() = default;
-
-#ifdef _GLIBCXX_HAVE_TLS
-  __future_base::_Async_state_common::~_Async_state_common() { _M_join(); }
-
-  // Explicit instantiation due to -fno-implicit-instantiation.
-  template void call_once(once_flag&, void (thread::*&&)(), reference_wrapper<thread>&&);
-  template _Bind_simple_helper<void (thread::*)(), reference_wrapper<thread>>::__type __bind_simple(void (thread::*&&)(), reference_wrapper<thread>&&);
-#endif
 #endif
 
 _GLIBCXX_END_NAMESPACE_VERSION
diff --git a/libstdc++-v3/testsuite/20_util/unique_ptr/54351.cc b/libstdc++-v3/testsuite/20_util/unique_ptr/54351.cc
new file mode 100644
index 00000000000..2565e62feb3
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/unique_ptr/54351.cc
@@ -0,0 +1,70 @@
+// { dg-options "-std=gnu++0x" }
+// { dg-do run }
+
+// Copyright (C) 2012 Free Software Foundation
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// 20.7.1 Template class unique_ptr [unique.ptr]
+
+#include <memory>
+#include <testsuite_hooks.h>
+
+struct A;
+
+struct B
+{
+  std::unique_ptr<A> a;
+};
+
+struct A
+{
+  B* b;
+  ~A() { VERIFY(b->a != nullptr); }
+};
+
+void test01()
+{
+  B b;
+  b.a.reset(new A);
+  b.a->b = &b;
+}
+
+struct C;
+
+struct D
+{
+  std::unique_ptr<C[]> c;
+};
+
+struct C
+{
+  D* d;
+  ~C() { VERIFY(d->c != nullptr); }
+};
+
+void test02()
+{
+  D d;
+  d.c.reset(new C[1]);
+  d.c[0].d = &d;
+}
+
+int main()
+{
+  test01();
+  test02();
+}
diff --git a/libstdc++-v3/testsuite/20_util/unique_ptr/assign/48635_neg.cc b/libstdc++-v3/testsuite/20_util/unique_ptr/assign/48635_neg.cc
index 1ed53ee2d5c..39cc8e1e55e 100644
--- a/libstdc++-v3/testsuite/20_util/unique_ptr/assign/48635_neg.cc
+++ b/libstdc++-v3/testsuite/20_util/unique_ptr/assign/48635_neg.cc
@@ -41,10 +41,10 @@ void f()
   std::unique_ptr<int, B&> ub(nullptr, b);
   std::unique_ptr<int, D&> ud(nullptr, d);
   ub = std::move(ud);
-// { dg-error "use of deleted function" "" { target *-*-* } 189 }
+// { dg-error "use of deleted function" "" { target *-*-* } 195 }
 
   std::unique_ptr<int[], B&> uba(nullptr, b);
   std::unique_ptr<int[], D&> uda(nullptr, d);
   uba = std::move(uda);
-// { dg-error "use of deleted function" "" { target *-*-* } 329 }
+// { dg-error "use of deleted function" "" { target *-*-* } 341 }
 }
diff --git a/libstdc++-v3/testsuite/23_containers/array/element_access/54388.cc b/libstdc++-v3/testsuite/23_containers/array/element_access/54388.cc
new file mode 100644
index 00000000000..a69a5edb6a0
--- /dev/null
+++ b/libstdc++-v3/testsuite/23_containers/array/element_access/54388.cc
@@ -0,0 +1,42 @@
+// { dg-options "-std=gnu++0x" }
+//
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <array>
+#include <testsuite_hooks.h>
+
+struct A
+{
+  bool valid = true;
+  ~A() { valid = false; }
+};
+
+void
+test01()
+{
+  bool test __attribute__((unused)) = true;
+
+  const std::array<A, 1> a;
+  const A& aa = a.at(0);
+  VERIFY(aa.valid);
+}
+
+int main()
+{
+  test01();
+}
diff --git a/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..9bdad10a9a5
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,27 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::binomial_distribution<int>;
+template class std::binomial_distribution<long>;
+template class std::binomial_distribution<unsigned int>;
+template class std::binomial_distribution<unsigned long>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/cauchy_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/cauchy_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..ad33135e789
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/cauchy_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::cauchy_distribution<float>;
+template class std::cauchy_distribution<double>;
+template class std::cauchy_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/chi_squared_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/chi_squared_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..626d538b264
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/chi_squared_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::chi_squared_distribution<float>;
+template class std::chi_squared_distribution<double>;
+template class std::chi_squared_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/discrete_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/discrete_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..2041218cb5d
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/discrete_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,27 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::discrete_distribution<int>;
+template class std::discrete_distribution<long>;
+template class std::discrete_distribution<unsigned int>;
+template class std::discrete_distribution<unsigned long>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/exponential_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/exponential_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..5addabcc3fa
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/exponential_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::exponential_distribution<float>;
+template class std::exponential_distribution<double>;
+template class std::exponential_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/extreme_value_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/extreme_value_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..02125e920fe
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/extreme_value_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::extreme_value_distribution<float>;
+template class std::extreme_value_distribution<double>;
+template class std::extreme_value_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/fisher_f_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/fisher_f_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..f6c62e9076b
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/fisher_f_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::fisher_f_distribution<float>;
+template class std::fisher_f_distribution<double>;
+template class std::fisher_f_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/gamma_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/gamma_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..c6ad617f679
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/gamma_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::gamma_distribution<float>;
+template class std::gamma_distribution<double>;
+template class std::gamma_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/geometric_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/geometric_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..7a8e31d9870
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/geometric_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,27 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::geometric_distribution<int>;
+template class std::geometric_distribution<long>;
+template class std::geometric_distribution<unsigned int>;
+template class std::geometric_distribution<unsigned long>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/lognormal_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/lognormal_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..20ba45838bf
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/lognormal_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::lognormal_distribution<float>;
+template class std::lognormal_distribution<double>;
+template class std::lognormal_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/negative_binomial_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/negative_binomial_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..36f48735008
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/negative_binomial_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,27 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::negative_binomial_distribution<int>;
+template class std::negative_binomial_distribution<long>;
+template class std::negative_binomial_distribution<unsigned int>;
+template class std::negative_binomial_distribution<unsigned long>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/normal_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/normal_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..9fe18ba6143
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/normal_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::normal_distribution<float>;
+template class std::normal_distribution<double>;
+template class std::normal_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/piecewise_constant_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/piecewise_constant_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..e2a04d771bd
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/piecewise_constant_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::piecewise_constant_distribution<float>;
+template class std::piecewise_constant_distribution<double>;
+template class std::piecewise_constant_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/piecewise_linear_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/piecewise_linear_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..d3b52a3ebf7
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/piecewise_linear_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::piecewise_linear_distribution<float>;
+template class std::piecewise_linear_distribution<double>;
+template class std::piecewise_linear_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/poisson_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/poisson_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..2f762a27a9b
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/poisson_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,27 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::poisson_distribution<int>;
+template class std::poisson_distribution<long>;
+template class std::poisson_distribution<unsigned int>;
+template class std::poisson_distribution<unsigned long>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/student_t_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/student_t_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..a11280b8359
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/student_t_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::student_t_distribution<float>;
+template class std::student_t_distribution<double>;
+template class std::student_t_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/uniform_int_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/uniform_int_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..b9851186365
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/uniform_int_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,27 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::uniform_int_distribution<int>;
+template class std::uniform_int_distribution<long>;
+template class std::uniform_int_distribution<unsigned int>;
+template class std::uniform_int_distribution<unsigned long>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/uniform_real_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/uniform_real_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..011fa34a49f
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/uniform_real_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::uniform_real_distribution<float>;
+template class std::uniform_real_distribution<double>;
+template class std::uniform_real_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/26_numerics/random/weibull_distribution/requirements/explicit_instantiation/1.cc b/libstdc++-v3/testsuite/26_numerics/random/weibull_distribution/requirements/explicit_instantiation/1.cc
new file mode 100644
index 00000000000..8e268ef80b8
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/weibull_distribution/requirements/explicit_instantiation/1.cc
@@ -0,0 +1,26 @@
+// { dg-do compile }
+// { dg-options "-std=c++11" }
+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2012 Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <random>
+
+template class std::weibull_distribution<float>;
+template class std::weibull_distribution<double>;
+template class std::weibull_distribution<long double>;
diff --git a/libstdc++-v3/testsuite/30_threads/async/54297.cc b/libstdc++-v3/testsuite/30_threads/async/54297.cc
new file mode 100644
index 00000000000..ff35a6778ab
--- /dev/null
+++ b/libstdc++-v3/testsuite/30_threads/async/54297.cc
@@ -0,0 +1,51 @@
+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }
+// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } }
+// { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } }
+// { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } }
+// { dg-require-cstdint "" }
+// { dg-require-gthreads "" }
+// { dg-require-atomic-builtins "" }
+// { dg-require-nanosleep "" }
+
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <chrono>
+#include <thread>
+#include <future>
+#include <set>
+#include <testsuite_hooks.h>
+
+struct Task;
+
+std::set<const Task*> dead_tasks;
+
+struct Task
+{
+  ~Task() { dead_tasks.insert(this); }
+
+  void operator()() const
+  {
+    std::this_thread::sleep_for(std::chrono::seconds(1));
+    VERIFY( dead_tasks.count(this) == 0 );
+  }
+};
+
+int main()
+{
+  std::async(std::launch::async, Task());
+}
diff --git a/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc b/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc
new file mode 100644
index 00000000000..57696708766
--- /dev/null
+++ b/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc
@@ -0,0 +1,62 @@
+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }
+// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } }
+// { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } }
+// { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } }
+// { dg-require-cstdint "" }
+// { dg-require-gthreads "" }
+
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <vector>
+#include <mutex>
+#include <condition_variable>
+#include <thread>
+
+// PR libstdc++/54185
+
+std::condition_variable* cond = nullptr;
+std::mutex mx;
+int started = 0;
+int constexpr NUM_THREADS = 10;
+
+void do_thread_a()
+{
+  std::unique_lock<std::mutex> lock(mx);
+  if(++started >= NUM_THREADS)
+  {
+    cond->notify_all();
+    delete cond;
+    cond = nullptr;
+  }
+  else
+    cond->wait(lock);
+}
+
+int main(){
+  std::vector<std::thread> vec;
+  for(int j = 0; j < 1000; ++j)
+  {
+    started = 0;
+    cond = new std::condition_variable;
+    for (int i = 0; i < NUM_THREADS; ++i)
+      vec.emplace_back(&do_thread_a);
+    for (int i = 0; i < NUM_THREADS; ++i)
+      vec[i].join();
+    vec.clear();
+  }
+}
diff --git a/libstdc++-v3/testsuite/Makefile.am b/libstdc++-v3/testsuite/Makefile.am
index 7094ad52991..0cf8de501c8 100644
--- a/libstdc++-v3/testsuite/Makefile.am
+++ b/libstdc++-v3/testsuite/Makefile.am
@@ -134,7 +134,7 @@ check-DEJAGNU $(check_DEJAGNU_normal_targets): check-DEJAGNU%: site.exp
 	  normal0) \
 	    if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
 	      $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
-			$(RUNTESTFLAGS) abi.exp; \
+			$(RUNTESTFLAGS) abi.exp prettyprinters.exp; \
 	    else echo "WARNING: could not find \`runtest'" 1>&2; :;\
 	    fi; \
 	    dirs="`cd $$srcdir; echo [013-9][0-9]_*/*`";; \
diff --git a/libstdc++-v3/testsuite/Makefile.in b/libstdc++-v3/testsuite/Makefile.in
index e433bb9effe..bb077d148a6 100644
--- a/libstdc++-v3/testsuite/Makefile.in
+++ b/libstdc++-v3/testsuite/Makefile.in
@@ -572,7 +572,7 @@ check-DEJAGNU $(check_DEJAGNU_normal_targets): check-DEJAGNU%: site.exp
 	  normal0) \
 	    if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
 	      $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
-			$(RUNTESTFLAGS) abi.exp; \
+			$(RUNTESTFLAGS) abi.exp prettyprinters.exp; \
 	    else echo "WARNING: could not find \`runtest'" 1>&2; :;\
 	    fi; \
 	    dirs="`cd $$srcdir; echo [013-9][0-9]_*/*`";; \
diff --git a/libstdc++-v3/testsuite/decimal/pr54036-1.cc b/libstdc++-v3/testsuite/decimal/pr54036-1.cc
new file mode 100644
index 00000000000..8514ab05cd6
--- /dev/null
+++ b/libstdc++-v3/testsuite/decimal/pr54036-1.cc
@@ -0,0 +1,70 @@
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-require-effective-target dfp }
+
+#include <decimal/decimal>
+#include <testsuite_hooks.h>
+
+using namespace std::decimal;
+
+decimal32
+__attribute__ ((noinline))
+my_nan32 (void)
+{
+  decimal32 z = 0;
+  decimal32 v = z/z;
+  return v;
+}
+
+decimal32
+__attribute__ ((noinline))
+my_inf32 (void)
+{
+  decimal32 o = 1;
+  decimal32 z = 0;
+  decimal32 v = o/z;
+  return v;
+}
+
+int
+main ()
+{
+  decimal32 v;
+
+  v = my_nan32 ();
+
+  VERIFY (__builtin_isnand32 (v.__getval ()));
+  VERIFY (!__builtin_signbitd32 (v.__getval ()));
+
+  v = -v;
+
+  VERIFY (__builtin_isnand32 (v.__getval ()));
+  VERIFY (__builtin_signbitd32 (v.__getval ()));
+
+  v = my_inf32 ();
+
+  VERIFY (__builtin_isinfd32 (v.__getval ()));
+  VERIFY (!__builtin_signbitd32 (v.__getval ()));
+
+  v = -v;
+
+  VERIFY (__builtin_isinfd32 (v.__getval ()));
+  VERIFY (__builtin_signbitd32 (v.__getval ()));
+
+  return 0;
+}
diff --git a/libstdc++-v3/testsuite/decimal/pr54036-2.cc b/libstdc++-v3/testsuite/decimal/pr54036-2.cc
new file mode 100644
index 00000000000..2a625d6884b
--- /dev/null
+++ b/libstdc++-v3/testsuite/decimal/pr54036-2.cc
@@ -0,0 +1,70 @@
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-require-effective-target dfp }
+
+#include <decimal/decimal>
+#include <testsuite_hooks.h>
+
+using namespace std::decimal;
+
+decimal64
+__attribute__ ((noinline))
+my_nan64 (void)
+{
+  decimal64 z = 0;
+  decimal64 v = z/z;
+  return v;
+}
+
+decimal64
+__attribute__ ((noinline))
+my_inf64 (void)
+{
+  decimal64 o = 1;
+  decimal64 z = 0;
+  decimal64 v = o/z;
+  return v;
+}
+
+int
+main ()
+{
+  decimal64 v;
+
+  v = my_nan64 ();
+
+  VERIFY (__builtin_isnand64 (v.__getval ()));
+  VERIFY (!__builtin_signbitd64 (v.__getval ()));
+
+  v = -v;
+
+  VERIFY (__builtin_isnand64 (v.__getval ()));
+  VERIFY (__builtin_signbitd64 (v.__getval ()));
+
+  v = my_inf64 ();
+
+  VERIFY (__builtin_isinfd64 (v.__getval ()));
+  VERIFY (!__builtin_signbitd64 (v.__getval ()));
+
+  v = -v;
+
+  VERIFY (__builtin_isinfd64 (v.__getval ()));
+  VERIFY (__builtin_signbitd64 (v.__getval ()));
+
+  return 0;
+}
diff --git a/libstdc++-v3/testsuite/decimal/pr54036-3.cc b/libstdc++-v3/testsuite/decimal/pr54036-3.cc
new file mode 100644
index 00000000000..0d74446623c
--- /dev/null
+++ b/libstdc++-v3/testsuite/decimal/pr54036-3.cc
@@ -0,0 +1,70 @@
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-require-effective-target dfp }
+
+#include <decimal/decimal>
+#include <testsuite_hooks.h>
+
+using namespace std::decimal;
+
+decimal128
+__attribute__ ((noinline))
+my_nan128 (void)
+{
+  decimal128 z = 0;
+  decimal128 v = z/z;
+  return v;
+}
+
+decimal128
+__attribute__ ((noinline))
+my_inf128 (void)
+{
+  decimal128 o = 1;
+  decimal128 z = 0;
+  decimal128 v = o/z;
+  return v;
+}
+
+int
+main ()
+{
+  decimal128 v;
+
+  v = my_nan128 ();
+
+  VERIFY (__builtin_isnand128 (v.__getval ()));
+  VERIFY (!__builtin_signbitd128 (v.__getval ()));
+
+  v = -v;
+
+  VERIFY (__builtin_isnand128 (v.__getval ()));
+  VERIFY (__builtin_signbitd128 (v.__getval ()));
+
+  v = my_inf128 ();
+
+  VERIFY (__builtin_isinfd128 (v.__getval ()));
+  VERIFY (!__builtin_signbitd128 (v.__getval ()));
+
+  v = -v;
+
+  VERIFY (__builtin_isinfd128 (v.__getval ()));
+  VERIFY (__builtin_signbitd128 (v.__getval ()));
+
+  return 0;
+}