diff options
| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-19 22:08:03 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-20 07:28:19 +0800 |
| commit | bb6028b40bf19db1b42bf8c68c35eb82f40043b7 (patch) | |
| tree | 7d5c90f9d16ced1952e52eb022edb68b7d959991 /ChangeLog | |
| parent | eaeaad3fcac4d7a30b5a256410cb59fa1a3fa9dd (diff) | |
RISC-V: Optimize constant AVL for LRA pattern
This optimization was discovered in the tuple move splitted bug fix patch.
Before this patch:
vsetivli zero,4,e16,mf2,ta,ma
lhu a3,96(a5)
vlseg8e16.v v1,(a5)
lw a4,%lo(e)(a2)
vsetvli a6,zero,e64,m2,ta,ma
addi a0,a7,8
vse16.v v1,0(a7)
vse16.v v2,0(a0)
addi a0,a0,8
vse16.v v3,0(a0)
addi a0,a0,8
vse16.v v4,0(a0)
addi a0,a0,8
vse16.v v5,0(a0)
addi a0,a0,8
vse16.v v6,0(a0)
addi a0,a0,8
vse16.v v7,0(a0)
addi a0,a0,8
vse16.v v8,0(a0)
After this patch:
vsetivli zero,4,e64,m2,ta,ma
addi a0,a7,8
vlseg8e16.v v1,(a5)
vse16.v v1,0(a7)
vse16.v v2,0(a0)
addi a0,a0,8
vse16.v v3,0(a0)
addi a0,a0,8
vse16.v v4,0(a0)
addi a0,a0,8
vse16.v v5,0(a0)
addi a0,a0,8
vse16.v v6,0(a0)
addi a0,a0,8
vse16.v v7,0(a0)
addi a0,a0,8
vse16.v v8,0(a0)
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/post-ra-avl.c: New test.
Diffstat (limited to 'ChangeLog')
0 files changed, 0 insertions, 0 deletions