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authorlaw <law@138bc75d-0d04-0410-961f-82ee72b054a4>1998-04-04 05:29:22 +0000
committerlaw <law@138bc75d-0d04-0410-961f-82ee72b054a4>1998-04-04 05:29:22 +0000
commit03725bf031ec9456e4e6afd9dc4ebd50fcccda1c (patch)
treef15eaa08e855cdbc68c60389f528daa3d081414f /gcc/config/alpha/alpha.md
parent5ca8d76e2ccecf6db2a30b1c37b567cc004d7af5 (diff)
gcc2 snapshot 980401 import
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc3@18982 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/alpha/alpha.md')
-rw-r--r--gcc/config/alpha/alpha.md22
1 files changed, 11 insertions, 11 deletions
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 1feddc5eb6d..f90a4dd59a0 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -1,5 +1,5 @@
;; Machine description for DEC Alpha for GNU C compiler
-;; Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+;; Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;; This file is part of GNU CC.
@@ -799,24 +799,24 @@
[(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
""
- "zapnot %1,1,%0"
- [(set_attr "type" "shift")])
+ "and %1,0xff,%0"
+ [(set_attr "type" "ilog")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
"TARGET_BWX"
"@
- zapnot %1,1,%0
+ and %1,0xff,%0
ldbu %0,%1"
- [(set_attr "type" "shift,ld")])
+ [(set_attr "type" "ilog,ld")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
"! TARGET_BWX"
- "zapnot %1,1,%0"
- [(set_attr "type" "shift")])
+ "and %1,0xff,%0"
+ [(set_attr "type" "ilog")])
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
@@ -829,16 +829,16 @@
(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
"TARGET_BWX"
"@
- zapnot %1,1,%0
+ and %1,0xff,%0
ldbu %0,%1"
- [(set_attr "type" "shift,ld")])
+ [(set_attr "type" "ilog,ld")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
"! TARGET_BWX"
- "zapnot %1,1,%0"
- [(set_attr "type" "shift")])
+ "and %1,0xff,%0"
+ [(set_attr "type" "ilog")])
(define_expand "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")