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authorJeff Law <jlaw@ventanamicro.com>2024-05-01 12:43:37 -0600
committerJeff Law <jlaw@ventanamicro.com>2024-05-01 12:43:37 -0600
commit76ca6e1f8b1524b82a871ce29cf58c79e5e77e2b (patch)
tree18c9532b6430f0202fe5cc004df55a9fd13240e2 /gcc/testsuite/g++.dg
parentfad93e7617ce1aafb006983a71b6edc9ae1eb2d1 (diff)
[committed] [RISC-V] Trivial pattern cleanup
As I was reviewing and cleaning up some internal work, I noticed a particular idiom being used elsewhere in the RISC-V backend. Specifically the use of explicit subregs when an adjustment to the match_operand would be sufficient. Let's take this example from the and-not splitter: > (define_split > [(set (match_operand:X 0 "register_operand") > (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand") > (subreg:QI (match_operand:X 2 "register_operand") 0))) > (const_int 1)))] Note the explicit subreg. We can instead use a match_operand with QImode. This ever-so-slightly simplifies the machine description. It also means that if we have a QImode object lying around (say we loaded it from memory in QImode), we can use it directly rather than first extending it to X, then truncing to QI. So we end up with simpler RTL and in rare cases improve the code we generate. When used in a define_split or define_insn_and_split we need to make suitable adjustments to the split RTL. Bootstrapped a while back. Just re-tested with a cross. gcc/ * config/riscv/bitmanip.md (splitter to use w-form division): Remove explicit subregs. (zero extended bitfield extraction): Similarly. * config/riscv/thead.md (*th_memidx_operand): Similarly.
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